Method for eliminating fake faults in gate-level simulation
AssigneeSilicon Motion, Inc.
InventorChia-Cheng PAI
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Abstract
A method for determining the propagation delay of each path in an integrated circuit is provided herein. The method includes determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement; determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement; and when the selected path exceeds the timing requirement in the path-based mode, lowering the cell delay of each cell in the selected path.
Claims20
A method for adjusting propagation delay of each path in an integrated circuit, comprising:
- determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement;
- determining, in a path-based mode, whether the propagation delay of the selected path exceeds the timing requirement;
- and
- when the selected path does not exceed the timing requirement in the path-based mode, lowering a cell delay in the worst-based mode of each cell in the selected path.
A non-transitory computer readable medium storing program code for determining a propagation delay of each path in an integrated circuit, the program code comprising a set of instructions, stored on the computer readable medium, that when executed by a computer, causes the computer to perform the following operations:
- determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement;
- determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement;
- and
- when the selected path does not exceed the timing requirement in the path-based mode, lowering a cell delay in the worst-based mode of each cell in the selected path.
Dependencies are inferred from the claim text.