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US 2022/0065930 A1Published application
Test access port with address and command capability
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
Claims20
A device comprising:
- (1) a clock input terminal;
- (2) a bidirectional data terminal;
- (3) a first circuit including:
- a first circuit clock input lead coupled to the clock input terminal;
- a bidirectional data lead coupled to the bidirectional data terminal;
- a first circuit data output lead;
- a first circuit data input lead;
- and
- a first circuit control output lead;
- (4) a second circuit operating in a plurality of states, the second circuit including:
- a second circuit data input lead coupled to the first circuit data output lead;
- a second circuit data output lead coupled to the first circuit data input lead;
- a second circuit clock input lead coupled to the clock input terminal;
- and
- a second circuit control input lead;
- (5) a third circuit including:
- a third circuit data input lead coupled to the first circuit data output lead;
- a third circuit control input lead coupled to the second circuit data output lead;
- and
- a third circuit clock input lead coupled to the clock input terminal and a third circuit enable output lead;
- and
- (6) a fourth circuit including:
- a fourth circuit control input lead coupled to the first circuit control output lead;
- a fourth circuit enable input lead coupled to the third circuit enable output lead;
- and
- a fourth circuit output control lead coupled to the second circuit control input lead.
23 more elements
An integrated circuit comprising:
- (a) a bidirectional terminal for input and output of a test data signal and input of a test mode signal;
- (b) a test clock terminal;
- (c) first TAP circuitry having a first test data in input, a first test clock input, a first test mode select input, and a first test data out output;
- (d) second TAP circuitry having a second test data in input, a second test clock input, a second test mode select input, and a second test data out output;
- (e) adaptor circuitry having an input node coupled to the bidirectional terminal, an input coupled to the test clock terminal, a test data out input, a test data in output and a test mode select output;
- (f) TAP state circuitry having inputs coupled to the test clock terminal and the test mode select output, and having state outputs;
- (g) command circuitry having inputs coupled to the test data in output and the state outputs, and having a command bus output that includes at least a first TAP select output and a second TAP select output;
- (h) first logic circuitry having an input coupled to the test mode select output, having an input coupled to the first TAP select output, and having an output coupled to the first test mode select input;
- (i) second logic circuitry having an input coupled to the test mode select output, having an input coupled to the second TAP select output, and having an output coupled to the second test mode select input;
- and
- (j) switch circuitry having:
- an input coupled to the test data in output;
- an output coupled to the test data out input;
- an output coupled to the first test data in input;
- an input coupled to the first test data out output;
- an output coupled to the second test data in input
- an input coupled to the second test data out output;
- and
- an input coupled to the command bus output.
16 more elements
Dependencies are inferred from the claim text.