Frequency doubler using recirculating delay circuit and method thereof

A frequency doubler comprising:

• a multiplexer configured to receive a first clock and output a second clock in accordance with a third clock, wherein the first clock has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase;
• a recirculating delay circuit configured to receive the second clock and output a fourth clock and a fifth clock;
• and
• a divide-by-two circuit configured to receive the fourth clock and output the third clock, wherein the recirculating delay circuit comprises a logic gate and a delay chain comprising a plurality of clock buffers including an intermediate clock buffer and a last clock buffer, said logic gate being configured to receive the second clock and the fifth clock and output a sixth clock, said plurality of clock buffers being cascaded and configured to receive the sixth clock and output the fourth clock from the intermediate clock buffer and output the fifth clock from the last clock buffer.