# US 2022/0046785 A1 · Flexible circuit board for chip on film and chip package comprising the same, and electronic device comprising the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0046785 A1 - Document ID: US20220046785A1 - Status: Published application - Kind: A1 - Application number: 17/384,892 - Filed: 2021-07-26 - Published: 2022-02-10 - Earliest claimed: 2020-08-04 - Assignees: LG Innotek Co., Ltd. - Applicants: LG Innotek Co., Ltd. - Inventors: Chae Won Kang; Jun Young Lim - Web page: https://patentgrep.com/patent/US20220046785A1 ## CPC - H05K 1/0206: {by printed thermal vias} - H05K 1/189: characterised by the use of flexible or folded printed circuits - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/688: {Flexible insulating substrates} - H05K 1/0209: {External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings} - H05K 2201/0338: Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer - H05K 2201/09736: Varying thickness of a single conductor; Conductors in the same plane having different thicknesses - H10W 72/265: {Providing thermal transfer, e.g. thermal bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A flexible circuit board for a chip on film according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface. ## Claims ### Claim 1 A flexible circuit board for a chip on film, the flexible circuit board comprising: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface. ### Claim 2 (depends on 1) The flexible circuit board of claim 1, wherein the heat dissipation pattern layer, the connection layer, and the heat dissipation layer are integrally formed. ### Claim 3 (depends on 1) The flexible circuit board of claim 1, wherein an area of the heat dissipation pattern layer is smaller than an area of the heat dissipation layer. ### Claim 4 (depends on 1) The flexible circuit board of claim 1, wherein the area of the heat dissipation pattern layer is 5% or more of an area of the chip. ### Claim 5 (depends on 1) The flexible circuit board of claim 1, wherein the heat dissipation pattern layer includes a first heat dissipation pattern layer and a second heat dissipation pattern layer spaced apart from each other, and the first heat dissipation pattern layer and the second heat dissipation pattern layer are connected to the same heat dissipation layer. ### Claim 6 (depends on 5) The flexible circuit board of claim 5, wherein the first heat dissipation pattern layer is connected to at least two or more of the connection layers. ### Claim 7 (depends on 1) The flexible circuit board of claim 1, further comprising a connection pattern layer that connects the circuit pattern layer and the heat dissipation pattern layer. ### Claim 8 (depends on 1) The flexible circuit board of claim 1, wherein the circuit pattern layer includes a first metal layer and a second metal layer on the first metal layer, and a thickness of the first metal layer is smaller than a thickness of the second metal layer. ### Claim 9 (depends on 1) The flexible circuit board of claim 1, wherein a thickness of the substrate is 5 μm to 100 μm. ### Claim 10 (depends on 1) The flexible circuit board of claim 1, wherein a thickness of the circuit pattern layer is 5 μm to 25 μm. ### Claim 11 (depends on 1) The flexible circuit board of claim 1, wherein the area of the heat dissipation pattern layer is 10% or more of an area of the chip mounting region. ### Claim 12 (depends on 1) The flexible circuit board of claim 1, wherein a first direction that is a longitudinal direction and a second direction that is a width direction of a chip disposed in the chip mounting region are defined, and a length in the first direction of the heat dissipation pattern layer is greater than a width in the second direction of the heat dissipation pattern layer. ### Claim 13 (depends on 1) The flexible circuit board of claim 1, wherein the first direction that is the longitudinal direction and the second direction that is the width direction of the chip disposed in the chip mounting region are defined, and a separation distance in the first direction of the hole is smaller than a separation distance in the second direction of the hole. ### Claim 14 (depends on 13) The flexible circuit board of claim 13, wherein a separation distance between the heat dissipation pattern layer and the circuit pattern layer in the second direction is greater than the separation distance in the second direction of the hole. ### Claim 15 (depends on 13) The flexible circuit board of claim 13, wherein the circuit pattern layer includes a plurality of circuit patterns, and a minimum separation distance between adjacent circuit patterns among the circuit patterns is smaller than the separation distance in the first direction of the hole. ### Claim 16 (depends on 12) The flexible circuit board of claim 12, wherein the width in the second direction of the heat dissipation pattern layer is greater than the separation between the heat dissipation pattern layer and the circuit pattern layer in the second direction. ### Claim 17 (depends on 12) The flexible circuit board of claim 12, wherein a ratio of the length in the first direction of the heat dissipation pattern layer to the width in the second direction of the heat dissipation pattern layer is 0.5 to 5 times a ratio of a length in the first direction to a width in the second direction of the chip. ### Claim 18 A chip package comprising: a substrate including a first surface and a second surface opposite to the first surface and including a chip mounting region; a circuit pattern layer disposed on the first surface; a chip electrically connected to the circuit pattern layer; and a heat dissipation part disposed in the chip mounting region, wherein the substrate is formed with at least two or more holes that are formed in a region overlapping the heat dissipation part, and the heat dissipation part includes: a heat dissipation pattern layer disposed on the first surface; a connection layer disposed inside the hole; and a heat dissipation layer disposed on the second surface, wherein the heat dissipation pattern layer, the connection layer, and the heat dissipation layer are integrally formed. ### Claim 19 (depends on 18) The chip package of claim 18, wherein the heat dissipation pattern layer and the chip are spaced apart from each other. ### Claim 20 (depends on 18) The chip package of claim 18, wherein the heat dissipation pattern layer and the chip are connected via bumps.