# US 2022/0045839 A1 · Methods for protecting computer hardware from cyber threats

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- Number: US 2022/0045839 A1
- Document ID: US20220045839A1
- Status: Published application
- Kind: A1
- Application number: 17/422,884
- Filed: 2020-01-16
- Published: 2022-02-10
- Earliest claimed: 2019-01-17
- Assignees: Fortifyiq, Inc.
- Applicants: Fortifyiq, Inc.
- Inventors: Ury KREIMER; Alexander KESLER; Vadim BUGAENKO; Yaacov BELENKY
- Web page: https://patentgrep.com/patent/US20220045839A1

## CPC

- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/003: {for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]}
- H04L 9/0618: {Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation}
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 2209/04: Masking or blinding
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A semiconductor intellectual property (IP) core comprising a transformation engine designed and configured to represent each element of a field GF(28) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter. Also disclosed in the specification are several other IP cores and several different methods.

## Claims

### Claim 1

A semiconductor intellectual property (IP) core comprising a transformation engine designed and configured to represent each element of a field GF(28) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter.

### Claim 2 (depends on 1)

An IP core according to claim 1, wherein d≥9.

### Claim 3 (depends on 2)

An IP core according to claim 2, wherein d≥24.

### Claim 4 (depends on 1)

An IP core according to claim 1, wherein said transformation engine represents a same field element by one of 2d various ways (pairwise differing by terms that are multiples of P(x)), and at each moment of calculations chooses any of said various representations.

### Claim at position 5

5-9. (canceled)

### Claim 10

A method of building different representations of the Galois Field (GF) implemented by logic circuitry comprising:
representing each element of a field GF(28) using a polynomial of degree no higher than 7+d, where d>0 is a redundancy parameter.

### Claim 11 (depends on 10)

A method according to claim 10, wherein d≥9.

### Claim 12 (depends on 11)

A method according to claim 11, wherein d≥24.

### Claim 13 (depends on 10)

A method according to claim 10, comprising representing a same field element by one of 2d various ways (pairwise differing by terms that are multiples of P(x)), and at each moment of calculations chooses any of said various representations.

### Claim at position 10

14-87. (canceled)