# US 2022/0045784 A1 · Additional Bit Freezing For Polar Coding

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- Number: US 2022/0045784 A1
- Document ID: US20220045784A1
- Status: Published application
- Kind: A1
- Application number: 17/365,965
- Filed: 2021-07-01
- Published: 2022-02-10
- Earliest claimed: 2020-08-10
- Assignees: Mediatek Inc.
- Applicants: MediaTek Inc.
- Inventors: Tun-Ping Huang; Wei-De Wu; Mao-Ching Chiu; Chia-Wei Tai; Tien-Yu Lin
- Web page: https://patentgrep.com/patent/US20220045784A1

## CPC

- H04L 1/1819: {with retransmission of additional or different redundancy}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/13: Linear codes
- H03M 13/27: using interleaving techniques
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/618: {Shortening and extension of codes}
- H03M 13/6306: {Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy (H03M13/3761, H03M13/3769 and H03M13/635 take precedence)}
- H03M 13/6362: {by puncturing}
- H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 1/0061: {Error detection codes}
- H04L 1/0068: {by puncturing}
- H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)}
- H04L 1/08: by repeating transmission, e.g. Verdan system {(H04L1/1858 and H04L1/189 take precedence)}
- H04L 1/1893: {Physical mapping arrangements (physical resource mapping in general H04L5/00)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

## Claims

### Claim 1

A method, comprising:
performing, by a processor of an apparatus, polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits; and
transmitting, by the processor, at least some of the subblocks of coded bits,
wherein the performing of the polar coding comprises:
performing encoder input bit mapping and freezing on the plurality of input subblocks;
additionally freezing one or more encoder input bit channels; and
rate-matching and subblock interleaving the plurality of input subblocks to result in one or more punctured bits, one or more shortened bits, and one or more output bits as the at least some of the subblocks of coded bits that are transmitted.

### Claim 2 (depends on 1)

The method of claim 1, wherein the performing of the polar coding comprises performing the polar coding in an incremental redundancy hybrid automatic repeat request (IR-HARQ) procedure, and wherein the transmitting comprises performing a retransmission in the IR-HARQ procedure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a largest index of punctured bits compared to indexes of punctured bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 4 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a smallest index of output bits compared to indexes of output bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 5 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a least indexed bit and having a size less than a threshold.

### Claim 6 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises setting information bits in one or more of the plurality of input subblocks for a retransmission to zero responsive to a number of the one or more punctured bits or a number of the one or more shortened bits for the retransmission being more than a portion of a polar mother code size used in polar coding for an initial transmission corresponding to the retransmission.

### Claim 7 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing smallest N/2 bit positions of the plurality of input subblocks responsive to a number of the one or more punctured bits being larger than N/2, and wherein N denotes a polar code size seen by a rate-matching interleaver that performs the rate-matching and subblock interleaving.

### Claim 8 (depends on 1)

The method of claim 1, wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing information bits of the plurality of input subblocks with indexes ranging from 0 to ┌4/3P┐−1, and wherein P denotes a number of punctured bits in the one or more subblocks of punctured bits.

### Claim 9

A method, comprising:
performing, by a processor of an apparatus, polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits; and
transmitting, by the processor, at least some of the subblocks of coded bits,
wherein the performing of the polar coding comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

### Claim 10 (depends on 9)

The method of claim 9, wherein the additionally freezing of one of the plurality of input subblocks comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a largest index of punctured bits compared to indexes of punctured bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 11 (depends on 9)

The method of claim 9, wherein the additionally freezing of one of the plurality of input subblocks comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a smallest index of output bits compared to indexes of output bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 12 (depends on 9)

The method of claim 9, wherein the performing of the polar coding comprises performing the polar coding in an incremental redundancy hybrid automatic repeat request (IR-HARQ) procedure, wherein the transmitting comprises performing a retransmission in the IR-HARQ procedure, and wherein the performing of the polar coding further comprises:
performing encoder input bit mapping and freezing on the plurality of input subblocks; and
rate-matching and subblock interleaving the plurality of input subblocks to result in one or more punctured bits, one or more shortened bits, and one or more output bits as the at least some of the subblocks of coded bits that are transmitted.

### Claim 13

An apparatus, comprising:
a transceiver configured to communicate wirelessly; and
a processor coupled to the transceiver and configured to perform operations comprising:
performing polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits; and
transmitting, via the transceiver, at least some of the subblocks of coded bits,
wherein, in performing the polar coding, the processor is configured to perform operations comprising:
performing encoder input bit mapping and freezing on the plurality of input subblocks;
additionally freezing one or more encoder input bit channels; and
rate-matching and subblock interleaving the plurality of input subblocks to result in one or more punctured bits, one or more shortened bits, and one or more output bits as the at least some of the subblocks of coded bits that are transmitted.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein, in performing the polar coding, the processor is configured to perform the polar coding in an incremental redundancy hybrid automatic repeat request (IR-HARQ) procedure, and wherein, in transmitting, the processor is configured to perform a retransmission in the IR-HARQ procedure.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to additionally freeze one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a largest index of punctured bits compared to indexes of punctured bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to additionally freeze one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a smallest index of output bits compared to indexes of output bits contained in other ones of the interleaved plurality of subblocks of coded bits.

### Claim 17 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to additionally freeze one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a least indexed bit and having a size less than a threshold.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to set information bits in one or more of the plurality of input subblocks for a retransmission to zero responsive to a number of the one or more punctured bits or a number of the one or more shortened bits for the retransmission being more than a portion of a polar mother code size used in polar coding for an initial transmission corresponding to the retransmission.

### Claim 19 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to additionally freeze smallest N/2 bit positions of the plurality of input subblocks responsive to a number of the one or more punctured bits being larger than N/2, and wherein N denotes a polar code size seen by a rate-matching interleaver that performs the rate-matching and subblock interleaving.

### Claim 20 (depends on 13)

The apparatus of claim 13, wherein, in additionally freezing the one or more encoder input bit channels, the processor is configured to additionally freeze information bits of the plurality of input subblocks with indexes ranging from 0 to ┌4/3P┐−1, and wherein P denotes a number of punctured bits in the one or more subblocks of punctured bits.
