# US 2022/0045701 A1 · Current mode logic driver and transmission driver including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045701 A1 - Document ID: US20220045701A1 - Status: Published application - Kind: A1 - Application number: 17/322,002 - Filed: 2021-05-17 - Published: 2022-02-10 - Earliest claimed: 2020-08-10 - Assignees: MagnaChip Semiconductor, Ltd. - Applicants: MagnaChip Semiconductor, Ltd. - Inventors: Gil Sung ROH; Sang Kyung KIM - Web page: https://patentgrep.com/patent/US20220045701A1 ## CPC - H04B 1/04: Circuits - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03F 2200/129: there being a feedback over the complete amplifier - H03F 2203/45702: the LC comprising two resistors - H04B 2001/045: {with means for improving efficiency} - H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} - H04B: TRANSMISSION - H03F: AMPLIFIERS - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively. ## Claims ### Claim 1 A transmission driver, comprising: a pulse generator configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal; and a current mode logic driver configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively. ### Claim 2 (depends on 1) The transmission driver of claim 1, further comprising a phase inverter configured to receive an input signal and output the first input signal and the second input signal to the pulse generator and the current mode logic driver, respectively. ### Claim 3 (depends on 2) The transmission driver of claim 2, wherein the phase inverter comprises: a first OP amp configured to generate the first input signal by buffering the input signal; and an inverting amplifier, comprising two resistors and a second OP amp, configured to generate the second input signal by inverting a phase of the first input signal. ### Claim 4 (depends on 1) The transmission driver of claim 1, wherein the current mode logic driver comprises: a first NMOS transistor, configured to receive the first input signal through a gate terminal, connected between a first output node and a third common node; a second NMOS transistor, configured to receive the second input signal through the gate terminal, connected between a second output node and the third common node; and a third NMOS transistor connected in series to the first and second NMOS transistors. ### Claim 5 (depends on 4) The transmission driver of claim 4, wherein the third NMOS transistor is turned on according to a bias control signal to flow a bias current activating the current mode logic driver. ### Claim 6 (depends on 5) The transmission driver of claim 5, wherein the current mode logic driver comprises: a first load controller, connected between the first output node and a power supply voltage, controlling the first load resistance value by receiving the first pulse signal; and a second load controller, connected between the second output node and the power supply voltage, controlling the second load resistance value by receiving the second pulse signal. ### Claim 7 (depends on 6) The transmission driver of claim 6, wherein the first load controller comprises: a first resistor having an end connected to the power supply voltage and another end connected to the first output node; a first variable resistor having an end connected to the power supply voltage; and a first PMOS transistor connecting the first pulse signal to the gate terminal, a source terminal to another end of the first variable resistor, and a drain terminal to the first output node. ### Claim 8 (depends on 7) The transmission driver of claim 7, wherein the second load controller comprises: a second resistor having an end connected to the power supply voltage and another end connected to the second output node; a second variable resistor having an end connected to the power supply voltage; and a second PMOS transistor connecting the second pulse signal to the gate terminal, the source terminal to another end of the second variable resistor, and the drain terminal to the second output node. ### Claim 9 (depends on 8) The transmission driver of claim 8, wherein the current mode logic driver further comprises third resistors connected between the first output node and the second output node. ### Claim 10 (depends on 9) The transmission driver of claim 9, wherein the first pulse signal generated in synchronization with the falling edge time point of the first input signal has a low level first section, and wherein the second pulse signal generated in synchronization with the falling edge time point of the second input signal has a low level second section. ### Claim 11 (depends on 10) The transmission driver of claim 10, wherein, in the first section, the first NMOS transistor and the second PMOS transistor are turned off in the first section, and the second NMOS transistor and the first PMOS transistor are turned on. ### Claim 12 (depends on 11) The transmission driver of claim 11, wherein, in the second section, the first NMOS transistor and the second PMOS transistor are turned on, and the second NMOS transistor and the first PMOS transistor are turned off. ### Claim 13 (depends on 12) The transmission driver of claim 12, wherein, in the first and second sections, the pre-emphasis signal is output by controlling the first and second load resistance values of the current mode logic driver. ### Claim 14 A current mode logic driver, comprising: a first load controller, controlled by a first pulse signal, connected to a power supply voltage; a second load controller, controlled by a second pulse signal, connected to the power supply voltage; a first NMOS transistor connected in series to the first load controller; a second NMOS transistor connected in series to the second load controller; and a third NMOS transistor connected in series to the first and second NMOS transistors. ### Claim 15 (depends on 14) The current mode logic driver of claim 14, wherein the first and second NMOS transistors are configured to receive first and second input signals having different levels. ### Claim 16 (depends on 15) The current mode logic driver of claim 15, wherein the third NMOS transistor is turned on according to a bias control signal to flow a bias current. ### Claim 17 (depends on 16) The current mode logic driver of claim 16, wherein the first load controller comprises: a first resistor having an end connected to the power supply voltage and another end connected to a first output node; a first variable resistor having an end connected to the power supply voltage; and a first PMOS transistor connecting the first pulse signal to a gate terminal, a source terminal to another end of the first variable resistor, and a drain terminal to the first output node. ### Claim 18 (depends on 17) The current mode logic driver of claim 17, wherein the second load controller comprises: a second resistor having an end connected to the power supply voltage and another end connected to a second output node; a second variable resistor having an end connected to the power supply voltage; and a second PMOS transistor connecting the second pulse signal to the gate terminal, the source terminal to another end of the second variable resistor, and the drain terminal to the second output node. ### Claim 19 (depends on 18) The current mode logic driver of claim 18, wherein the first pulse signal generated in synchronization with a falling edge time point of the first input signal has a low level first section, and wherein the second pulse signal generated in synchronization with a falling edge time point of the second input signal has a low level second section. ### Claim 20 (depends on 19) The current mode logic driver of claim 19, wherein a pre-emphasis signal to which pre-emphasis technique has been applied is output by variable resistor control of the first and second load controllers in the first and second sections. ### Claim 21 A transmission driver, comprising: a pulse generator configured to synchronize at a falling edge time point of a first input signal to generate a first pulse signal, and at a falling edge time point of a second input signal to generate a second pulse signal; and a current mode logic driver, comprising: a first load controller, controlled by the first pulse signal, connected to a power supply voltage; and a second load controller, controlled by the second pulse signal, connected to the power supply voltage. ### Claim 22 (depends on 21) The transmission driver of claim 21, wherein the current mode logic driver further comprises a first NMOS transistor connected in series to the first load controller, a second NMOS transistor connected in series to the second load controller, and a third NMOS transistor connected in series to the first and second NMOS transistors. ### Claim 23 (depends on 21) The transmission driver of claim 21, wherein the current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively. ### Claim 24 (depends on 21) The transmission driver of claim 21, further comprising a phase inverter configured to receive an input signal and output the first input signal and the second input signal to the pulse generator and the current mode logic driver, respectively. ### Claim 25 (depends on 24) The transmission driver of claim 24, wherein the phase inverter comprises: a first OP amp configured to generate the first input signal by buffering the input signal; and an inverting amplifier, comprising two resistors and a second OP amp, configured to generate the second input signal by inverting a phase of the first input signal.