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US 2022/0045691 A1Published application
System and method to compensate for feedback delays in digital class-d modulators
AssigneeAnalog Devices, Inc.
InventorsAdam R. SPIRER, Abhishek BANDYOPADHYAY
Life of this patent
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Abstract
Systems and method for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.
Claims20
An architecture for a class D modulator, comprising:
- an input line for receiving an input signal;
- a summer configured to subtract a feedback signal from the input signal and generate a summer output;
- a loop filter configured to receive the summer output and produce a filtered output;
- a quantizer configured to quantize the filtered output and output a quantized signal;
- a main feedback loop from the quantizer to the summer configured to filter the quantized signal to generate the feedback signal;
- and
- a quantizer feedback loop around the quantizer including a first filter, configured to generate a filtered quantized signal, wherein the filtered quantized signal is added back into the quantizer.
4 more elements
A method for a class D modulator, comprising:
- receiving an input signal;
- subtracting a feedback signal from the input signal at a summer to generate a summer output;
- filtering the summer output at a loop filter to generate a filtered output;
- quantizing the filtered output at a quantizer and outputting a quantized signal;
- in a main feedback loop:
- filtering the quantized signal to generate the feedback signal;
- and
- feeding back the feedback signal to the summer;
- wherein filtering the quantized signal and feeding back the feedback signal includes adding a main feedback loop delay, and wherein the main feedback loop delay is one or more clock cycles;
- and
- in a quantizer feedback loop:
- filtering the quantized signal to generate a filtered quantized signal;
- and
- feeding back the filtered quantized signal to the quantizer.
11 more elements
An architecture for a class D modulator, comprising:
- an input line for receiving an input signal;
- a summer configured to subtract a feedback signal from the input signal and generate a summer output;
- a loop filter configured to receive the summer output and produce a filtered output;
- a quantizer configured to quantize the filtered output and output a quantized signal;
- and
- a main feedback loop from the quantizer to the summer configured to filter the quantized signal to generate the feedback signal, wherein the main feedback loop has a delay of one or more clock cycles.
3 more elements
Dependencies are inferred from the claim text.