# US 2022/0045673 A1 · Off chip driving system and signal compensation method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045673 A1 - Document ID: US20220045673A1 - Status: Published application - Kind: A1 - Application number: 17/155,046 - Filed: 2021-01-21 - Published: 2022-02-10 - Earliest claimed: 2020-08-05 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Chang-Ting WU - Web page: https://patentgrep.com/patent/US20220045673A1 ## CPC - H03K 17/161: {in field-effect transistor switches} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 17/164: {using parallel switching arrangements} - H03K 17/22: Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) - H03K 19/01721: {by means of a pull-up or down element} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An off chip driving system includes a decision circuit, multiple first and second adjustable-enhancement circuits, and multiple first and second drivers. The decision circuit outputs a first and a second decision signal according to a clock and an input data. Each first adjustable-enhancement circuit generates one of first control signals in response to the first and the second decision signal and one of first optional signals. Each second adjustable-enhancement circuit generates one of second control signals in response to the first and the second decision signal and one of second optional signals. Each first driver is coupled to the corresponding first adjustable-enhancement circuit and configured to be enabled in response to the corresponding first control signal. Each second driver is coupled to the corresponding second adjustable-enhancement circuit and configured to be enabled in response to the corresponding second control signal. ## Claims ### Claim 1 An off chip driving system, comprising: a decision circuit, configured to output a first decision signal and a second decision signal according to a clock and an input data; a plurality of first adjustable enhancement circuits, coupled to the decision circuit, wherein each first adjustable enhancement circuit is configured to generate one of a plurality of first control signals in response to the first decision signal, the second decision signal and one of a plurality of first optional signals; and a pull-up circuit, comprising a plurality of first drivers, wherein each first driver is coupled to a corresponding one of the first adjustable enhancement circuits and configured to be enabled in response to a corresponding one of the first control signals. ### Claim 2 (depends on 1) The off chip driving system of claim 1, wherein the decision circuit is configured to generate a pulse with a high level as the first decision signal when the input data turns from a first level to a second level, and to generate a pulse with a low level as the second decision signal when the input data turns from the second level to the first level. ### Claim 3 (depends on 1) The off chip driving system of claim 1, wherein when the first decision signal and the second decision signal are both at a low level, the first adjustable enhancement circuits provide a system high voltage as all the first control signals, so that all the first drivers turn off, when the first decision signal and the second decision signal are both at a high level, the first adjustable enhancement circuits provide a system low voltage as all the first control signals, so that all the first drivers turn on. ### Claim 4 (depends on 1) The off chip driving system of claim 1, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the first adjustable enhancement circuits provide the first optional signals as the first control signals respectively, so that a part of the first drivers turn off and the other part of the first drivers turn on. ### Claim 5 (depends on 1) The off chip driving system of claim 1, wherein each one of the first adjustable enhancement circuits comprises: a first multiplexer, configured to receive the first decision signal, a system low voltage and an enabling signal, to output the first decision signal when the enabling signal is at a high level, and to output the system low voltage when the enabling signal is at a low level; a second multiplexer, configured to receive the second decision signal, a system high voltage and the enabling signal, to output the second decision signal when the enabling signal is at the high level, and to output the system high voltage when the enabling signal is at the low level; and a third multiplexer, coupled to the first multiplexer and the second multiplexer, configured to receive the system low voltage, the system high voltage, the corresponding one of the first optional signals, a third decision signal from the first multiplexer and a fourth decision signal from the second multiplexer, and configured to output the corresponding one of the first control signals in response to the third decision signal and the fourth decision signal. ### Claim 6 (depends on 5) The off chip driving system of claim 5, wherein the third multiplexer is configured to output the system low voltage as the corresponding first control signal when the third decision signal and the fourth decision signal are at the high level, to output the system high voltage as the corresponding first control signal when the third decision signal and the fourth decision signal are at the low level, and to output the corresponding first optional signal when the third decision signal is at the low level and the fourth decision signal is at the high level. ### Claim 7 (depends on 1) The off chip driving system of claim 1, wherein the first drivers are PMOS. ### Claim 8 An off chip driving system, comprising: a decision circuit, configured to output a first decision signal and a second decision signal according to a clock and an input data; a plurality of second adjustable enhancement circuits, coupled to the decision circuit, wherein each second adjustable enhancement circuit is configured to generate one of a plurality of second control signals in response to the first decision signal, the second decision signal and one of a plurality of second optional signals; a pull-down circuit, comprising a plurality of second drivers, wherein each second driver is coupled to a corresponding one of the second adjustable enhancement circuits and configured to be enabled in response to a corresponding one of the second control signals. ### Claim 9 (depends on 8) The off chip driving system of claim 8, wherein the decision circuit is configured to generate a pulse with a high level as the first decision signal when the input data turns from a first level to a second level, and to generate a pulse with a low level as the second decision signal when the input data turns from the second level to the first level. ### Claim 10 (depends on 8) The off chip driving system of claim 8, wherein when the first decision signal and the second decision signal are both at a low level, the second adjustable enhancement circuits provide a system high voltage as all the second control signals, so that all the second drivers turn on, when the first decision signal and the second decision signal are both at a high level, the second adjustable enhancement circuits provide a system low voltage as all the second control signals, so that all the second drivers turn off. ### Claim 11 (depends on 8) The off chip driving system of claim 8, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the second adjustable enhancement circuits provide the second optional signals as the second control signals respectively, so that a part of the second drivers turn off and the other part of the second drivers turn on. ### Claim 12 (depends on 8) The off chip driving system of claim 8, wherein each one of the second adjustable enhancement circuits comprises: a first multiplexer, configured to receive the first decision signal, a system low voltage and an enabling signal, to output the first decision signal when the enabling signal is at a high level, and to output the system low voltage when the enabling signal is at a low level; a second multiplexer, configured to receive the second decision signal, a system high voltage and the enabling signal, to output the second decision signal when the enabling signal is at the high level, and to output the system high voltage when the enabling signal is at the low level; and a third multiplexer, coupled to the first multiplexer and the second multiplexer, configured to receive the system low voltage, the system high voltage, the corresponding one of the second optional signals, a third decision signal from the first multiplexer and a fourth decision signal from the second multiplexer, and configured to output the corresponding one of the second control signals in response to the third decision signal and the fourth decision signal. ### Claim 13 (depends on 12) The off chip driving system of claim 12, wherein the third multiplexer is configured to output the system low voltage as the second control signal when the third decision signal and the fourth decision signal are at the high level, to output the system high voltage as the second control signal when the third decision signal and the fourth decision signal are at the low level, and to output the second optional signal when the third decision signal is at the low level and the fourth decision signal is at the high level. ### Claim 14 (depends on 8) The off chip driving system of claim 8, wherein the second drivers are NMOS. ### Claim 15 An off chip driving system, comprising: a decision circuit, configured to output a first decision signal and a second decision signal according to a clock and an input data; a first adjustable enhancement circuit, coupled to the decision circuit, wherein the first adjustable enhancement circuit is configured to generate a first control signal in response to the first decision signal, the second decision signal and a first optional signal; a second adjustable enhancement circuit, coupled to the decision circuit, wherein the second adjustable enhancement circuit is configured to generate a second control signal in response to the first decision signal, the second decision signal and a second optional signal; a pull-up circuit, configured to be enabled in response to the first control signal; and a pull-down circuit configured to be enabled in response to the second control signal. ### Claim 16 An off chip driving system, comprising: a decision circuit, configured to output a first decision signal and a second decision signal according to a clock and an input data; a plurality of adjustable enhancement circuits, coupled to the decision circuit, wherein each adjustable enhancement circuit is configured to generate one of a plurality of control signals in response to the first decision signal, the second decision signal and one of a plurality of optional signals; and a driving circuit, comprising a plurality of drivers, wherein each driver is coupled to a corresponding one of the adjustable enhancement circuits and configured to be enabled in response to a corresponding one of the control signals. ### Claim 17 (depends on 16) The off chip driving system of claim 16, wherein the decision circuit is configured to generate a pulse with a high level as the first decision signal when the input data turns from a first level to a second level, and to generate a pulse with a low level as the second decision signal when the input data turns from the second level to the first level. ### Claim 18 (depends on 16) The off chip driving system of claim 16, wherein when the first decision signal and the second decision signal are both at a low level, the adjustable enhancement circuits provide a system high voltage as all the control signals, so that all the drivers turn off, when the first decision signal and the second decision signal are both at a high level, the adjustable enhancement circuits provide a system low voltage as all the control signals, so that all the drivers turn on. ### Claim 19 (depends on 16) The off chip driving system of claim 16, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the adjustable enhancement circuits provide the optional signals as the control signals respectively, so that a part of the drivers turn off and the other part of the drivers turn on. ### Claim 20 (depends on 16) The off chip driving system of claim 16, wherein when the first decision signal and the second decision signal are both at a low level, the adjustable enhancement circuits provide a system high voltage as all the control signals, so that all the drivers turn on, when the first decision signal and the second decision signal are both at a high level, the adjustable enhancement circuits provide a system low voltage as all the control signals, so that all the drivers turn off. ### Claim 21 (depends on 16) The off chip driving system of claim 16, wherein when the first decision signal is at a low level and the second decision signal is at a high level, the adjustable enhancement circuits provide the optional signals as the control signals respectively, so that a part of the drivers turn off and the other part of the drivers turn on. ### Claim 22 (depends on 16) The off chip driving system of claim 16, wherein each one of the adjustable enhancement circuits comprises: a first multiplexer, configured to receive the first decision signal, a system low voltage and an enabling signal, to output the first decision signal when the enabling signal is at a high level, and to output the system low voltage when the enabling signal is at a low level; a second multiplexer, configured to receive the second decision signal, a system high voltage and the enabling signal, to output the second decision signal when the enabling signal is at the high level, and to output the system high voltage when the enabling signal is at the low level; and a third multiplexer, coupled to the first multiplexer and the second multiplexer, configured to receive the system low voltage, the system high voltage, the corresponding one of the optional signals, a third decision signal from the first multiplexer and a fourth decision signal from the second multiplexer, and configured to output the corresponding one of the control signals in response to the third decision signal and the fourth decision signal. ### Claim 23 (depends on 22) The off chip driving system of claim 22, wherein the third multiplexer is configured to output the system low voltage as the corresponding control signal when the third decision signal and the fourth decision signal are at the high level, to output the system high voltage as the corresponding control signal when the third decision signal and the fourth decision signal are at the low level, and to output the corresponding optional signal when the third decision signal is at the low level and the fourth decision signal is at the high level. ### Claim 24 (depends on 16) The off chip driving system of claim 16, wherein the drivers are PMOS. ### Claim 25 (depends on 16) The off chip driving system of claim 16, wherein the drivers are NMOS.