# US 2022/0045671 A1 · Drive circuit, drive method, and semiconductor system

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- Number: US 2022/0045671 A1
- Document ID: US20220045671A1
- Status: Published application
- Kind: A1
- Application number: 17/452,404
- Filed: 2021-10-27
- Published: 2022-02-10
- Earliest claimed: 2018-04-03
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Masashi AKAHANE
- Web page: https://patentgrep.com/patent/US20220045671A1

## CPC

- H03K 17/0822: {in field-effect transistor switches}
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 1/32: Means for protecting converters other than automatic disconnection
- H03K 17/18: Modifications for indicating state of switch
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H02M 1/327: {against abnormal temperatures}
- H03K 17/08: Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0081: Power supply means, e.g. to the switch driver
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A drive circuit includes: a control section generating a control signal; a first level shift section raising a level of a signal from the control section; a high side drive section controlling a semiconductor device; and a second level shift section lowering a level of a signal from the high side drive section for input to the control section. The high side drive section has an error detection section maintaining an output of an error detection signal when the semiconductor device is in an error status until a release signal is input, the control section has an error handling section outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section, and the error detection section stops the output of the error detection signal when the release signal is input.

## Claims

### Claim 1

A drive circuit of a semiconductor device comprising:
a control section configured to output (i) a control signal in accordance with an input signal and (ii) a release signal when an error detection signal is input thereto;
a first level shift section configured to raise a level of the control signal and a level of the release signal input from the control section;
a high side drive section configured to control the semiconductor device based on the control signal of which the level has been raised by the first level shift section; and
a second level shift section configured to lower a level of a signal from the high side drive section for input to the control section, wherein
the high side drive section has an error detection section configured to output the error detection signal when the semiconductor device is in an error status, and maintain the output of the error detection signal until the release signal of which the level has been raised by the first level shift section is input,
the control section has:
a control signal generation section configured to generate the control signal in accordance with the input signal;
an error handling section configured to generate the release signal when the error detection signal is input via the second level shift section; and
a first selection section configured to receive the control signal from the control signal generation section and the release signal from the error handling section, select either the control signal or the release signal, and output the selected signal to the first level shift section, and
the error detection section stops the output of the error detection signal when the release signal of which the level has been raised by the first level shift section is input.

### Claim 2 (depends on 1)

The drive circuit according to claim 1, wherein
the high side drive section further has a drive control section configured to drive the semiconductor device based on the control signal of which the level has been raised, and
the drive control section is configured to control the semiconductor device to be in Off-state when the error detection section outputs the error detection signal.

### Claim 3 (depends on 1)

The drive circuit according to claim 1, wherein
when the release signal is received from the error handling section, the first selection section selects the release signal and outputs the selected release signal to the first level shift section.

### Claim 4 (depends on 1)

The drive circuit according to claim 1, wherein
the control signal generation section generates, in accordance with the input signal, the control signal which includes a set pulse signal having a pulse indicating a timing for causing the semiconductor device to transition to On-state, and a reset pulse signal having a pulse indicating a timing for causing the semiconductor device to transition to Off-state,
the high side drive section further has a first latch section configured to receive the set pulse signal, the reset pulse signal, and the release signal, levels of the set pulse signal, the reset pulse signal, and the release signal having been raised by the first level shift section, and
the first latch section (i) generates the control signal having a logical value H for causing the semiconductor device to transition to the On-state when the first latch section receives the set pulse signal of which the level has been raised by the first level shift section and (ii) generates the control signal having a logical value L for causing the semiconductor device to transition to the Off-state when the first latch section receives the reset pulse signal or the release signal of which the level has been raised by the first level shift section.

### Claim 5 (depends on 4)

The drive circuit according to claim 4, wherein
the control signal generated by the first latch section is input to the error detection section.

### Claim 6 (depends on 5)

The drive circuit according to claim 5, wherein
when the control signal having the logical value L for causing the semiconductor device to transition to the Off-state is input to the error detection section, the error detection section stops the output of the error detection signal.

### Claim 7 (depends on 4)

The drive circuit according to claim 4, wherein
when the release signal is received from the error handling section, the first selection section outputs, to the first level shift section, the release signal instead of the reset pulse signal and does not output the set pulse signal.

### Claim 8 (depends on 4)

The drive circuit according to claim 4, wherein
the high side drive section further has a periodic pulse generation section configured to convert, for input to the second level shift section, the error detection signal output by the error detection section into an error detection pulse signal having a periodic pulse, and
the control section further has a second latch section configured to latch the error detection pulse signal for input to the error handling section.

### Claim 9 (depends on 1)

A semiconductor system comprising:
the semiconductor device; and
the drive circuit according to claim 1, the drive circuit controlling the semiconductor device.

### Claim 10

A drive method of driving a semiconductor device using a drive circuit including: a control section configured to output (i) a control signal in accordance with an input signal and (ii) a release signal when an error detection signal is input thereto; a first level shift section configured to raise a level of the control signal and a level of the release signal input from the control section; a high side drive section configured to control the semiconductor device based on the control signal of which the level has been raised by the first level shift section; and a second level shift section configured to lower a level of a signal from the high side drive section for input to the control section, the drive method comprising:
outputting, from an error detection section included in the high side drive section, the error detection signal when the semiconductor device is in an error status, and maintaining the output of the error detection signal until the release signal of which the level has been raised by the first level shift section is input;
generating, in the control section, the control signal in accordance with the input signal;
generating, in the control section, the release signal when the error detection signal is input to the control section via the second level shift section:
selecting either the control signal or the release signal and outputting the selected signal to the first level shift section from the control section; and
stopping the output of the error detection signal when the release signal of which the level has been raised by the first level shift section is input to the error detection section.