# US 2022/0045650 A1 · High linearity low noise amplifier

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- Number: US 2022/0045650 A1
- Document ID: US20220045650A1
- Status: Published application
- Kind: A1
- Application number: 16/988,705
- Filed: 2020-08-09
- Published: 2022-02-10
- Earliest claimed: 2020-08-09
- Assignees: Shenzhen Goodix Technology Co., Ltd.
- Applicants: Shenzhen Goodix Technology Co., Ltd.
- Inventors: Mostafa Elmala; Ahmed Emira; Mohamed Aboudina
- Web page: https://patentgrep.com/patent/US20220045650A1

## CPC

- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/193: with field-effect devices (H03F3/195 takes precedence)
- H03F 1/3205: {in field-effect transistor amplifiers}
- H03F 1/3217: {in single ended push-pull amplifiers}
- H03F 1/3223: {using feed-forward (H03F1/3211 takes precedence)}
- H03F 3/195: in integrated circuits
- H03F 3/3022: {CMOS common source output SEPP amplifiers (H03F3/3008 takes precedence)}
- H03F 2200/135: there being a feedback over one or more internal stages in the global amplifier
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2200/372: Noise reduction and elimination in amplifier
- H03F 2200/42: the input to the amplifier being made by capacitive coupling means
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/48: the output of the amplifier being coupled out by a capacitor
- H03F 2200/75: the amplifier stage being a common source configuration MOSFET
- H03F: AMPLIFIERS

## Abstract

An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

## Claims

### Claim 1

An amplifier circuit, comprising:
an input terminal configured to receive an input signal;
an output terminal configured to transmit an output signal;
a first signal path comprising a first amplifying circuit, wherein the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and wherein the first amplified output includes first amplifier circuit harmonic noise;
a second signal path comprising a second amplifying circuit, wherein the second amplifying circuit is configured to receive the input signal and to transmit a second amplified output to the output terminal, and wherein the second amplified output includes second amplifier circuit harmonic noise,
wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

### Claim 2 (depends on 1)

The amplifier circuit of claim 1, further comprising an input capacitor, configured to couple the input signal to each of the first and second signal paths.

### Claim 3 (depends on 1)

The amplifier circuit of claim 1, further comprising an input capacitor, configured to couple the input signal to each of the first and second amplifying circuits.

### Claim 4 (depends on 1)

The amplifier circuit of claim 1, wherein the first amplifying circuit comprises a first inverting circuit, and wherein the second amplifying circuit comprises a second inverting circuit.

### Claim 5 (depends on 4)

The amplifier circuit of claim 4, wherein:
the first inverting circuit comprises:
a first inverter input,
a first inverter output, and
a first feedback component connected to the first inverter input and to the first inverter output; and
the second inverting circuit comprises:
a second inverter input,
a second inverter output, and
a second feedback component connected to the second inverter input and to the second inverter output.

### Claim 6 (depends on 5)

The amplifier circuit of claim 5, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output, and
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output, and
one or more second NMOS devices connected to the second inverter output,
wherein a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices, and
wherein a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices.

### Claim 7 (depends on 5)

The amplifier circuit of claim 5, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output, and
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output, and
one or more second NMOS devices connected to the second inverter output,
wherein a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices, and
wherein a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices.

### Claim 8 (depends on 1)

The amplifier circuit of claim 1, wherein:
the first signal path comprises a first output capacitor, wherein the first output capacitor is configured to couple the first amplified output to the output terminal; and
the second signal path comprises a second output capacitor, wherein the second output capacitor is configured to couple the second amplified output to the output terminal.

### Claim 9

A method of using an amplifier circuit, the method comprising:
with an input terminal, receiving an input signal;
with an output terminal, transmitting an output signal;
with a first amplifying circuit of a first signal path, receiving the input signal;
with the first amplifying circuit, transmitting a first amplified output to the output terminal, wherein the first amplified output includes first amplifier circuit harmonic noise;
with a second amplifying circuit of a second signal path, receiving the input signal;
with the second amplifying circuit, transmitting a second amplified output to the output terminal, wherein the second amplified output includes second amplifier circuit harmonic noise;
wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

### Claim 10 (depends on 9)

The method of claim 9, further comprising, with an input capacitor, coupling the input signal to each of the first and second signal paths.

### Claim 11 (depends on 9)

The method of claim 9, further comprising, with an input capacitor, coupling the input signal to each of the first and second amplifying circuits.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first amplifying circuit comprises a first inverting circuit, and wherein the second amplifying circuit comprises a second inverting circuit.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the first inverting circuit comprises:
a first inverter input,
a first inverter output, and
a first feedback component connected to the first inverter input and to the first inverter output; and
the second inverting circuit comprises:
a second inverter input,
a second inverter output, and
a second feedback component connected to the second inverter input and to the second inverter output.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output, and
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output, and
one or more second NMOS devices connected to the second inverter output,
wherein a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices, and
wherein a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices.

### Claim 15 (depends on 13)

The method of claim 13, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output,
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output,
one or more second NMOS devices connected to the second inverter output,
wherein a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices, and
wherein a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices.

### Claim 16 (depends on 9)

The method of claim 9, further comprising:
with a first output capacitor of the first signal path, coupling the first amplified output to the output terminal; and
with a second output capacitor of the second signal path, coupling the second amplified output to the output terminal.

### Claim 17

A receiver circuit, comprising:
a low noise amplifier circuit (LNA), comprising:
an input terminal configured to receive an input signal,
an output terminal configured to transmit an output signal,
a first signal path comprising a first amplifying circuit, wherein the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and wherein the first amplified output includes first amplifier circuit harmonic noise,
a second signal path comprising a second amplifying circuit, wherein the second amplifying circuit is configured to receive the input signal and to transmit a second amplified output to the output terminal, and wherein the second amplified output includes second amplifier circuit harmonic noise,
wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal;
an analog-to-digital converter (ADC) configured to receive an analog signal based on the output signal of the LNA, and to generate a digital signal based on the received analog signal; and
a controller, configured to receive the digital signal.

### Claim 18 (depends on 17)

The receiver of claim 17, wherein the first amplifying circuit comprises a first inverting circuit, and wherein the second amplifying circuit comprises a second inverting circuit, wherein:
the first inverting circuit comprises:
a first inverter input,
a first inverter output, and
a first feedback component connected to the first inverter input and to the first inverter output; and
the second inverting circuit comprises:
a second inverter input,
a second inverter output, and
a second feedback component connected to the second inverter input and to the second inverter output.

### Claim 19 (depends on 18)

The receiver of claim 18, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output, and
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output, and
one or more second NMOS devices connected to the second inverter output,
wherein a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices, and
wherein a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices.

### Claim 20 (depends on 18)

The receiver of claim 18, wherein:
the first inverting circuit comprises:
one or more first PMOS devices connected to the first inverter output, and
one or more first NMOS devices connected to the first inverter output; and
the second inverting circuit comprises:
one or more second PMOS devices connected to the second inverter output, and
one or more second NMOS devices connected to the second inverter output,
wherein a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices, and
wherein a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices.