# US 2022/0045601 A1 · Method for controlling fault using switching technique of three phase four wire interlinking converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045601 A1 - Document ID: US20220045601A1 - Status: Published application - Kind: A1 - Application number: 17/466,182 - Filed: 2021-09-03 - Published: 2022-02-10 - Earliest claimed: 2020-08-04 - Assignees: Research & Business Foundation Sungkyunkwan University - Applicants: Research & Business Foundation Sungkyunkwan University - Inventors: Chung Yuen WON; Kwang Su NA; Mi Na KIM; Bong Yeon CHOI; Kyoung Min KANG; Hoon LEE; Chang Gyun AN; Tae Gyu KIM; Jun Sin YI - Web page: https://patentgrep.com/patent/US20220045601A1 ## CPC - H02M 1/32: Means for protecting converters other than automatic disconnection - H02M 7/53876: {based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times} - H02M 1/325: {with means for allowing continuous operation despite a fault, i.e. fault tolerant converters} - H02M 7/53875: {with analogue control of three-phase output} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault. ## Claims ### Claim 1 A method for controlling fault of a three phase four wire interlinking converter, the method comprising: obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane, wherein a signal having a phase difference of 120 degrees is converted into a signal having a phase difference of 90 degrees.; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and allocating, in the occurrence of the fault, a zero voltage vector to the area related to the fault, wherein a symmetric space vector voltage modulation method is applied to determine an order of providing the zero voltage vector, wherein the symmetric space vector voltage modulation method refers to a method in which the effective voltage vector exists in the center of one period after modulation and a zero voltage vector is applied before and after the effective voltage vector for a specific time, wherein the specific time is determined based on a combination of six effective voltage vectors and two zero voltage vectors selected in the occurrence of a line-to-line short circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein the determining an area related to a fault comprises generating a space vector using an effective vector and a zero vector selected based on an output voltage vector and a switching state of a switching component, wherein the space vector are generated for each sector area; and calculating a reference voltage for each sector area based on the space vector. ### Claim 3 (depends on 2) The method of claim 2, wherein the each sector area is composed of six areas on a voltage vector plane, and the six areas are divided by two sections having different sizes, and wherein the reference voltage is calculated based on a magnitude of vector selected in a clockwise direction. ### Claim 4 (depends on 3) The method of claim 3, wherein a voltage vector selected for each of a U-V line-to-line short circuit, a U-W line-to-line short circuit and a V-W line-to-line short circuit has a different value one another. ### Claim 5 (depends on 1) The method of claim 1, wherein the determining an area related to a fault determines the area related to the fault based on switching state of the output voltage vectors, and wherein the switching state means an on/off combination of a switching component controlled separately by the respective output phases of the three phase AC power source. ### Claim 6 (depends on 5) The method of claim 5, wherein the switching component turns on switches by applying vectors in a first order for a first sampling period, and turns off the switches by applying the in the reverse order of the first order for the second sampling period. ### Claim 7 A three phase four wire interlinking converter system, the system comprising: an inverter converting DC power to three phase AC power and outputting the three phase AC power; and a processor controlling switching components included in the inverter to control the three phase output AC power separately for each phase, wherein the processor is configured to: obtain a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; convert the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtain an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane, wherein a signal having a phase difference of 120 degrees is converted into a signal having a phase difference of 90 degrees; determine occurrence of a fault and an area related to the fault based on the output voltage vector; and allocate, in the occurrence of the fault, a zero voltage vector to the area related to the fault, wherein a symmetric space vector voltage modulation method is applied to determine an order of providing the zero voltage vector, wherein the symmetric space vector voltage modulation method refers to a method in which the effective voltage vector exists in the center of one period after modulation and a zero voltage vector is applied before and after the effective voltage vector for a specific time, wherein the specific time is determined based on a combination of six effective voltage vectors and two zero voltage vectors selected in the occurrence of a line-to-line short circuit. ### Claim 8 (depends on 7) The system of claim 7, wherein the processor is configured to generate a space vector using an effective vector and a zero vector selected based on an output voltage vector and a switching state of a switching component, wherein the space vector are generated for each sector area; and calculate a reference voltage for each sector area based on the space vector. ### Claim 9 (depends on 8) The system of claim 8, wherein the each sector area is composed of six areas on a voltage vector plane, and the six areas are divided by two sections having different sizes, and wherein the reference voltage is calculated based on a magnitude of vector selected in a clockwise direction. ### Claim 10 (depends on 9) The system of claim 9, wherein a voltage vector selected for each of a U-V line-to-line short circuit, a U-W line-to-line short circuit and a V-W line-to-line short circuit has a different value one another. ### Claim 11 (depends on 7) The system of claim 7, wherein the processor is configured to determine the area related to the fault based on switching state of the output voltage vectors, and wherein the switching state means an on/off combination of a switching component controlled separately by the respective output phases of the three phase AC power source. ### Claim 12 (depends on 11) The system of claim 11, wherein the switching component turns on switches by applying vectors in a first order for a first sampling period, and turns off the switches by applying the in the reverse order of the first order for the second sampling period.