# US 2022/0045302 A1 · Display device and organic light-emitting diode panel thereof, and method for manufacturing organic light-emitting diode panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045302 A1 - Document ID: US20220045302A1 - Status: Published application - Kind: A1 - Application number: 17/416,497 - Filed: 2020-11-25 - Published: 2022-02-10 - Earliest claimed: 2019-11-29 - Assignees: Boe Technology Group Co., Ltd. - Applicants: BOE Technology Group Co., Ltd. - Inventors: Pan XU; Yicheng LIN; Ling WANG; Guoying WANG; Xing ZHANG; Ying HAN - Web page: https://patentgrep.com/patent/US20220045302A1 ## CPC - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10K 59/1201: {Manufacture or treatment} - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10K 59/8792: {comprising light absorbing layers, e.g. black layers} - H10K 2102/351: {Thickness} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract The present disclosure provides a display device and an OLED panel thereof, and a method for manufacturing an OLED panel. The OLED panel includes: a substrate (10), and a light-emitting structure (11) disposed on the substrate (10), wherein at least one film layer (12) and a planarization layer disposed on the at least one film layer (12) are disposed between the substrate (10) and the light-emitting structure (11); the OLED panel comprises a first region (12a) and a second region (12b), wherein a source (124a) and a drain (124b) of the transistor are disposed in the first region (12a); wherein the at least one film layer (12) comprises an insulating layer, wherein a thickness of the insulating layer in the first region (12a) is less than a thickness of the insulating layer in the second region (12b). According to the embodiments of the present disclosure, the global flatness of the at least one film layer is improved, thereby improving the planarization effect of the planarization layer, and further improving the quality of the organic light-emitting layer and the brightness uniformity of the sub-pixels. ## Claims ### Claim 1 An organic light-emitting diode (OLED) panel, comprising: a substrate, and a light-emitting structure disposed on the substrate; wherein at least one film layer and a planarization layer disposed on the at least one film layer are disposed between the substrate and the light-emitting structure, the at least one film layer comprising a transistor; the OLED panel comprises a first region and a second region, wherein a source and a drain of the transistor are disposed in the first region; and wherein the at least one film layer comprises an insulating layer, wherein a thickness of the insulating layer in the first region is less than a thickness of the insulating layer in the second region. ### Claim 2 (depends on 1) The OLED panel according to claim 1, wherein the insulating layer comprises an interlayer dielectric layer and/or a passivation layer. ### Claim 3 (depends on 2) The OLED panel according to claim 2, wherein along a direction facing away from the substrate, the at least one film layer sequentially comprises: a bottom gate, a gate insulating layer, an active layer, the interlayer dielectric layer, the source, the drain, and the passivation layer. ### Claim 4 (depends on 3) The OLED panel according to claim 3, wherein the interlayer dielectric layer and/or the passivation layer is disposed only in the second region. ### Claim 5 (depends on 3) The OLED panel according to claim 3, wherein a thickness of the interlayer dielectric layer in the first region is less than a thickness of the interlayer dielectric layer in the second region, and/or a thickness of the passivation layer in the first region is less than a thickness of the passivation layer in the second region. ### Claim 6 (depends on 2) The OLED panel according to claim 2, wherein along a direction facing away from the substrate, the at least one film layer sequentially comprises: an active layer, a gate insulating layer, a top gate, the interlayer dielectric layer, the source, the drain, and the passivation layer. ### Claim 7 (depends on 6) The OLED panel according to claim 6, wherein the interlayer dielectric layer and/or the passivation layer is disposed only in the second region. ### Claim 8 (depends on 6) The OLED panel according to claim 6, wherein a thickness of the interlayer dielectric layer in the first region is less than a thickness of the interlayer dielectric layer in the second region, and/or a thickness of the passivation layer in the first region is less than a thickness of the passivation layer in the second region. ### Claim 9 (depends on 1) The OLED panel according to claim 1, wherein the at least one film layer comprises at least two transistors, and the first region further comprises a region where a connecting line between two of the at least two transistors is disposed. ### Claim 10 (depends on 1) The OLED panel according to claim 1, wherein the at least one film layer comprises pixel drive circuits configured to drive the light-emitting structure to emit light, and/or the at least one film layer comprises connecting lines connecting the pixel drive circuits. ### Claim 11 (depends on 1) The OLED panel according to claim 1, wherein the at least one film layer comprises a light shielding layer. ### Claim 12 (depends on 1) The OLED panel according to claim 1, wherein the first region comprises N sub-regions, the second region comprises M sub-regions, N+M≥3, and the thickness of the insulating layer in any two of the N+M sub-regions is different. ### Claim 13 (depends on 1) The OLED panel according to claim 1, wherein along a direction facing away from the substrate, the at least one film layer sequentially comprises: a bottom gate, a gate insulating layer, an active layer, the interlayer dielectric layer, the source, the drain, and the passivation layer; the at least one film layer comprises at least two transistors, and the first region further comprises a region where a connecting line between two of the at least two transistors is disposed; the at least one film layer comprises pixel drive circuits configured to drive the light-emitting structure to emit light, and/or the at least one film layer comprises connecting lines connecting the pixel drive circuits; the at least one film layer comprises a light shielding layer; and the first region comprises N sub-regions, the second region comprises M sub-regions, N+M≥3, and the thickness of the insulating layer in any two of the N+M sub-regions is different. ### Claim 14 A display device, comprising an organic light-emitting diode (OLED) panel comprising: a substrate, and a light-emitting structure disposed on the substrate; wherein at least one film layer and a planarization layer disposed on the at least one film layer are disposed between the substrate and the light-emitting structure, the at least one film layer comprising a transistor; the OLED panel comprises a first region and a second region, wherein a source and a drain of the transistor are disposed in the first region; and wherein the at least one film layer comprises an insulating layer, wherein a thickness of the insulating layer in the first region is less than a thickness of the insulating layer in the second region. ### Claim 15 A method for manufacturing an organic light-emitting diode (OLED) panel, comprising: providing a substrate; forming at least one film layer on the substrate, wherein the at least one film layer comprises a transistor, the OLED panel comprises a first region and a second region, a source and a drain of the transistor being disposed in the first region, and the at least one film layer comprises an insulating layer, wherein a thickness of the insulating layer in the first region is less than a thickness of the insulating layer in the second region; forming a planarization layer on the at least one film layer; and forming a light-emitting structure on the planarization layer. ### Claim 16 (depends on 15) The method according to claim 15, wherein the insulating layer comprises an interlayer dielectric layer; and forming the at least one film layer on the substrate comprises: sequentially forming a bottom gate, a gate insulating layer, an active layer, and the interlayer dielectric layer on the substrate; removing or thinning the interlayer dielectric layer in the first region, and forming, in the interlayer dielectric layer, through holes exposing a source region and a drain region; and filling the through holes with a conductive material, and forming a source and a drain on the interlayer dielectric layer. ### Claim 17 (depends on 15) The method according to claim 15, wherein the insulating layer comprises an interlayer dielectric layer; and forming the at least one film layer on the substrate comprises: sequentially forming an active layer, a gate insulating layer, a top gate, and the interlayer dielectric layer on the substrate; removing or thinning the interlayer dielectric layer in the first region, and forming, in the interlayer dielectric layer and the gate insulating layer, through holes exposing a source region and a drain region; and filling the through holes with a conductive material, and forming a source and a drain on the interlayer dielectric layer. ### Claim 18 (depends on 16) The method according to claim 16, wherein the insulating layer further comprises a passivation layer; and forming the at least one film layer on the substrate further comprises: forming the passivation layer on the source, the drain, and the interlayer dielectric layer; and removing or thinning the passivation layer in the first region. ### Claim 19 (depends on 15) The method according to claim 15, wherein the insulating layer comprises a passivation layer; and forming the at least one film layer on the substrate comprises: sequentially forming a bottom gate, a gate insulating layer, an active layer, and an interlayer dielectric layer on the substrate; forming, in the interlayer dielectric layer, through holes exposing a source region and a drain region; filling the through holes with a conductive material, and forming a source and a drain on the interlayer dielectric layer; forming the passivation layer on the source, the drain, and the interlayer dielectric layer; and removing or thinning the passivation layer in the first region; or forming the at least one film layer on the substrate comprises: sequentially forming an active layer, a gate insulating layer, a top gate, and an interlayer dielectric layer on the substrate; forming, in the interlayer dielectric layer and the gate insulating layer, through holes exposing a source region and a drain region; filling the through holes with a conductive material, and forming a source and a drain on the interlayer dielectric layer; forming the passivation layer on the source, the drain, and the interlayer dielectric layer; and removing or thinning the passivation layer in the first region. ### Claim 20 (depends on 15) The method according to claim 15, wherein the first region comprises: a first sub-region, and sub-regions from a second sub-region to an Nth sub-region, and the second region comprises: an (N+1)th sub-region, and sub-regions from an (N+2)th sub-region to an (N+M)th sub-region, N+M≥3; wherein the first sub-region is a region where a level difference is greater than a first predetermined level difference, the second sub-region is a region where the level difference is greater than a second predetermined level difference and less than or equal to the first predetermined level difference, the third sub-region is a region where the level difference is greater than a third predetermined level difference and less than or equal to the second predetermined level difference, and the (N+M)th sub-region is a region where the level difference is greater than an (N+M)th predetermined level difference and less than or equal to an (N+M−1)th predetermined level difference, wherein the first predetermined level difference, and the second predetermined level difference to the (N+M)th predetermined level difference gradually decrease; and forming the at least one film layer on the substrate comprises: processing the insulating layer with a semi-transparent mask plate to completely remove the insulating layer in the first sub-region, and remove part of the thickness of the insulating layer in the second sub-region, the third sub-region to the (N+M)th sub-region, wherein the thickness of the insulating layer removed from the second sub-region, the third sub-region to the (N+M)th sub-region gradually decreases.