# US 2022/0045271 A1 · Patterning oxidation resistant electrode in crossbar array circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045271 A1 - Document ID: US20220045271A1 - Status: Published application - Kind: A1 - Application number: 17/508,660 - Filed: 2021-10-22 - Published: 2022-02-10 - Earliest claimed: 2019-05-23 - Assignees: TetraMem Inc. - Applicants: TetraMem Inc. - Inventors: Minxian Zhang; Ning Ge - Web page: https://patentgrep.com/patent/US20220045271A1 ## CPC - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD} - H10N 70/028: {by conversion of electrode material, e.g. oxidation} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/841: {Electrodes} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer. ## Claims ### Claim 1 A method of manufacturing an RRAM-based crossbar array circuit comprising: providing a substrate; forming a bottom electrode on the substrate; forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide by a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status of the bottom electrode oxide and the solid status of the bottom electrode oxide by a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and forming a top electrode on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein the first plasma comprises an oxygen plasma. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the second plasma comprises an argon plasma. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the thermal process comprises heating under a temperature between 350° C. and 450° C. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the substrate is made of a material selected from Si, SiO2, Si3N4, Al2O3, AN, or glass. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein the bottom electrode layer is made of an oxidation resistance conductive material comprising Pt, Pd, Ir, a combinations thereof, or an alloy or other conductive materials thereof. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein the bottom electrode layer is made of a material selected from a Ti/Pt layer, a Ti/Pd layer, or a Ti/(Pt, Pd) layer. ### Claim 8 (depends on 1) The method as claim 1, wherein a thickness of the bottom electrode layer is between 10 nanometers and 30 nanometers. ### Claim 9 (depends on 1) The method as claimed in claim 1, wherein a material of the top electrode comprises Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, a combination thereof, or an alloy with any other conductive materials thereof. ### Claim 10 (depends on 1) The method as claimed in claim 1, wherein a material of the filament forming layer comprises TaOx (where x≤2.5), HfOx (where x≤2), TiOx(where x≤2), ZrOx (where x≤2), or a combination thereof. ### Claim 11 (depends on 1) The method as claimed in claim 1, further comprises: forming an inter-layer dielectric layer or a thermal oxide layer on the substrate before forming the bottom electrode on the substrate, wherein a material of the thermal oxide layer comprises SiO2. ### Claim 12 (depends on 1) The method as claimed in claim 1, wherein forming a patterned mask layer on the bottom electrode layer comprises: forming a mask layer on the bottom electrode layer; forming a photo resist layer on the mask layer; patterning the photo resist layer to be a patterned photo resist layer; etching the mask layer by reactive-ion etching or ion-etch via the patterned photo resist layer to form the patterned mask layer; and removing the patterned photo resist layer. ### Claim 13 (depends on 12) The method as claimed in claim 12, wherein a material of the mask layer comprises SiO2. ### Claim 14 (depends on 13) The method as claimed in claim 13, wherein a density of the mask layer is lower than that of the thermal oxide layer. ### Claim 15 (depends on 1) The method as claimed in claim 1, further comprises: connecting the patterned bottom electrode to a first row wire; and connecting the top electrode to a first column wire.