# US 2022/0045211 A1 · Semiconductor device and manufacturing method for the same

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- Number: US 2022/0045211 A1
- Document ID: US20220045211A1
- Status: Published application
- Kind: A1
- Application number: 17/511,014
- Filed: 2021-10-26
- Published: 2022-02-10
- Earliest claimed: 2017-09-18
- Assignees: Denso Corporation
- Applicants: Denso Corporation
- Inventors: Yuichi TAKEUCHI; Yasuhiro EBIHARA; Masahiro SUGIMOTO; Yusuke YAMASHITA
- Web page: https://patentgrep.com/patent/US20220045211A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10D 62/159: {Shapes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

## Claims

### Claim at position 1

1-8. (canceled)

### Claim 9

A manufacturing method for a semiconductor device including a semiconductor element of inversion type, the method comprising:
preparing a substrate made of semiconductor and having a first conductivity type or a second conductivity type;
forming a drift layer above the substrate, wherein the drift layer is made of semiconductor, has the first conductivity type, and has an impurity concentration smaller than the substrate;
forming an electric field block layer above the drift layer, wherein the electric field block layer is made of semiconductor and has the second conductivity type;
forming a plurality of trenches arranged in a stripe manner in the electric field block layer so that a longer direction of a respective trench is one direction, and thereafter, forming a plurality of JFET portions by providing semiconductor of the first conductivity type in the plurality of trenches, thereby forming a saturation current suppression layer which includes a plurality of electric field block layers arranged in a stripe manner and the plurality of JFET portions arranged in a stripe manner, wherein: a longer direction of a respective JFET portion is the one direction; a longer direction of a respective electric field block layers is the one direction; and the electric field block layers and the JFET portions are alternately arranged;
forming a current dispersion layer above the saturation current suppression layer, wherein the current dispersion layer is made of semiconductor, has the first conductivity type, and has a first conductivity type impurity concentration larger than the drift layer;
forming a base region above the saturation current suppression layer, wherein the base region is made of semiconductor and has the second conductivity type;
forming a source region above the base region, wherein the source region is made of semiconductor, has the first conductivity type, and has a first conductivity type impurity concentration larger than the drift layer;
forming a plurality of trench gate structures, including
forming a plurality of gate trenches which are from a surface of the source region and deeper than the base region and which are arranged in a stripe manner, wherein a longer direction of a respective gate trench intersects with the one direction; and
forming a gate insulating film on an inner wall surface of a respective gate trench and forming a gate electrode on the gate insulating film;
forming a source electrode electrically connected to the source region; and
forming a drain electrode on a back side of the substrate,
wherein:
forming the plurality of JFET portions includes
forming: a first layer located at a bottom surface and a side surface of the trench and having a first conductivity type impurity concentration larger than the drift layer; and a second layer located above the first layer and having a first conductivity type impurity concentration smaller than the drift layer.

### Claim 10 (depends on 9)

The manufacturing method according to claim 9, wherein:
forming the electric field block layer includes:
as the electric field block layer, epitaxially growing an lower layer portion and an upper layer portion continuously, wherein the lower layer portion contacts with the drift layer and the upper layer portion has a second conductivity type impurity concentration larger than the lower layer portion.

### Claim 11 (depends on 10)

The manufacturing method according to claim 10, wherein:
forming the electric field block layer is performed so that the lower layer portion has the second conductivity type impurity concentration that gradually increases in a direction from the drift layer to the upper layer portion.

### Claim 12 (depends on 9)

The manufacturing method according to claim 9, wherein:
forming the JFET portions and forming the current dispersion layer are performed continuously;
epitaxial growth of the first layer and the second layer of the JFET portion are performed continuously; and
epitaxial growth of the current dispersion layer is performed at the same time as the epitaxial growth of the second layer is performed.

### Claim 13 (depends on 9)

The manufacturing method according to claim 9, wherein:
forming the JFET portions includes:
epitaxially growing the first layer and the second layer of the JFET portion continuously; and thereafter, by planarization, removing portions of the first layer and the second layer outside the trench, whereby the first layer and the second layer are formed only in the trench; and
forming the current dispersion layer includes:
forming the current dispersion layer above the first layer and the second layer formed only in the trench and above the electric field block layer.

### Claim 14 (depends on 9)

The manufacturing method according to claim 9, further comprising:
forming a deep trench that, from a surface of the source region, penetrates the base region and the current dispersion layer and reaches the electric field block layer; and
forming a connection layer in the deep trench, wherein the connection layer has the second conductivity type and connects the base region and the electric field block layer.

### Claim 15 (depends on 12)

The manufacturing method according to claim 12, further comprising:
after forming the current dispersion layer and before forming the base region, forming a connection layer reaching the electric field block layer by performing ion implantation of second conductivity type impurity into the current dispersion layer; and
after forming the source region, forming a second conductivity type plug layer reaching the base region by performing ion implantation of second conductivity type impurity into the source region.