# US 2022/0045199 A1 · Controlling Fin-Thinning Through Feedback

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- Number: US 2022/0045199 A1
- Document ID: US20220045199A1
- Status: Published application
- Kind: A1
- Application number: 17/452,178
- Filed: 2021-10-25
- Published: 2022-02-10
- Earliest claimed: 2019-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd
- Inventors: Tsu-Hui Su; Chun-Hsiang Fan; Yu-Wen Wang; Ming-Hsi Yeh; Kuo-Bin Huang
- Web page: https://patentgrep.com/patent/US20220045199A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/642: {Chemical etching}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

## Claims

### Claim 1

A method comprising:
forming a first semiconductor fin and a second semiconductor fin protruding higher than isolation regions, wherein the isolation regions are on opposing sides of the first semiconductor fin and the second semiconductor fin;
determining a first target width of the first semiconductor fin and a second target width of the second semiconductor fin;
performing a first thinning process on the first semiconductor fin to achieve the first target width, wherein in the first thinning process, both of the first semiconductor fin and the second semiconductor fin are thinned, and the first semiconductor fin is thinned more than the second semiconductor fin; and
performing a second thinning process on the second semiconductor fin to achieve the second target width, wherein in second thinning process, both of the first semiconductor fin and the second semiconductor fin are thinned, and the second semiconductor fin is thinned more than the first semiconductor fin.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
before the first thinning process, measuring a first fin width of the first semiconductor fin; and
generating an etch recipe based on a difference between the first fin width and the first target width, wherein the first thinning process is performed using the etch recipe.

### Claim 3 (depends on 2)

The method of claim 2, wherein the generating the etching recipe comprises:
determining an etching time of the first thinning process based on the difference.

### Claim 4 (depends on 2)

The method of claim 2, wherein the generating the etching recipe comprises:
determining a temperature of the first thinning process based on the difference.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
etching a semiconductor substrate to form a first semiconductor strip and a second semiconductor strip and to form and trenches extending into the semiconductor substrate; and
forming the isolation regions filling the trenches.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
recessing the isolation regions to form the first semiconductor fin and the second semiconductor fin, respectively, wherein the first thinning process is performed after the isolation regions are recessed; and
after the first thinning process, forming a dummy gate stack on the first semiconductor fin.

### Claim 7 (depends on 6)

The method of claim 6 further comprising:
forming gate spacers on opposite sides of the dummy gate stack;
removing the dummy gate stack to form a recess between the gate spacers; and
performing an additional thinning process to thin the first semiconductor fin through the recess.

### Claim 8 (depends on 1)

The method of claim 1, wherein in the first thinning process, a ratio of a first etching rate ratio of the first semiconductor fin to a second etching rate of the second semiconductor fin is greater than about 5.

### Claim 9 (depends on 8)

The method of claim 8, wherein in the second thinning process, a ratio of a third etching rate of the second semiconductor fin to a fourth etching rate of the first semiconductor fin is greater than about 5.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first thinning process is performed through wet etching.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first semiconductor fin and the second semiconductor fin comprise different semiconductor materials.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first thinning process is performed using a first etching chemical, and the second thinning process is performed using a second etching chemical comprising:
the first etching chemical; and
an oxidant, wherein the first etching chemical is free from the oxidant.

### Claim 13

A method comprising:
forming a first semiconductor fin protruding higher than first isolation regions on opposite sides of the first semiconductor fin;
forming a second semiconductor fin protruding higher than second isolation regions on opposite sides of the second semiconductor fin;
measuring a first fin width of the first semiconductor fin;
measuring a second fin width of the second semiconductor fin;
thinning the first semiconductor fin based on the first fin width using a first etching chemical, wherein when the first semiconductor fin is thinned, the second semiconductor fin is also thinned, and a first etching rate of the first semiconductor fin is greater than a second etching rate of the second semiconductor fin; and
forming a dummy gate stack on the first semiconductor fin that has been thinned by the thinning the first semiconductor fin.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
thinning the second semiconductor fin based on the second fin width, wherein when the second semiconductor fin is thinned, the first semiconductor fin is also thinned, and a third etching rate of the second semiconductor fin is greater than a fourth etching rate of the first semiconductor fin.

### Claim 15 (depends on 13)

The method of claim 13 further comprising:
after the first semiconductor fin is thinned, measuring a third fin width of the first semiconductor fin; and
further thinning the first semiconductor fin based on the third fin width.

### Claim 16 (depends on 13)

The method of claim 13 further comprising:
adjusting a concentration of the first etching chemical based on the first fin width.

### Claim 17

A method comprising:
etching a semiconductor substrate to form a semiconductor region, with sidewalls of the semiconductor region being exposed;
thinning the semiconductor region;
after the semiconductor region is thinned, filling trenches on opposing sides of the etched semiconductor region to form isolation regions; and
recessing the isolation regions, so that a top portion of the semiconductor region protrudes higher than the isolation regions to form a first semiconductor fin.

### Claim 18 (depends on 17)

The method of claim 17, wherein when the etching the semiconductor substrate is finished, the semiconductor region protrudes above a top surface of a bulk portion of the semiconductor substrate, and the top surface is exposed to an etching chemical used for etching the semiconductor region.

### Claim 19 (depends on 17)

The method of claim 17, wherein when the first semiconductor fin is thinned, a second semiconductor fin formed of a different semiconductor material from the first semiconductor fin is also thinned.

### Claim 20 (depends on 17)

The method of claim 17, wherein the etching the semiconductor region is performed using a wet etching process.