# US 2022/0045196 A1 · Uniform interfacial layer on vertical fin sidewalls of vertical transport field-effect transistors

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- Number: US 2022/0045196 A1
- Document ID: US20220045196A1
- Status: Published application
- Kind: A1
- Application number: 17/506,770
- Filed: 2021-10-21
- Published: 2022-02-10
- Earliest claimed: 2019-02-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Shogo Mochizuki; ChoongHyun Lee; Kangguo Cheng; Juntao Li
- Web page: https://patentgrep.com/patent/US20220045196A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first portion proximate top surfaces thereof and a second portion below the first portion;
a top spacer disposed on sidewalls of the first portion of the one or more vertical fins; and
an interfacial layer disposed on sidewalls of the second portion of the one or more vertical fins;
wherein the one or more vertical fins provide vertical transport channels for one or more vertical transport field-effect transistors.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first top spacers protect the interfacial layer such that the interfacial layer has a uniform thickness.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising a gate stack disposed over the interfacial layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the gate stack comprises:
a gate dielectric layer having an inverted-L shape profile proximate the top surface of the one or more vertical fins; and
a gate conductor layer having an inverted-L shape profile below the inverted-L shape profile of the gate dielectric layer, a top surface of the gate conductor layer being below a top surface of the gate dielectric layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the inverted-L shape profile of the gate dielectric layer comprises:
a first vertically oriented portion adjacent sidewalls of the interfacial layer; and
a first horizontally oriented portion extending from an upper portion of the first vertically oriented portion below a bottom surface of the top spacer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the inverted-L shape profile of the gate conductor layer comprises:
a second vertically oriented portion adjacent sidewalls of the first vertically oriented portion of the gate dielectric layer; and
a second horizontally oriented portion extending from an upper portion of the second vertically oriented portion of the gate conductor layer below a bottom surface of the first horizontally oriented portion of the gate dielectric layer.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein at least a portion of a top surface of the second horizontally oriented portion of the gate conductor layer is exposed by the first horizontally oriented portion of the gate dielectric layer.

### Claim 8 (depends on 4)

The semiconductor structure of claim 4, further comprising a gate encapsulation layer surrounding at least a first portion of the gate conductor layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the top spacer comprises spacer material in a divot space defined between the gate encapsulation layer and a second portion of the gate conductor layer.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a bottom source/drain region disposed over the top surface of the substrate and surrounding a first portion of the sidewalls of the second portion of the one or more vertical fins;
a bottom spacer disposed over a top surface of the bottom source/drain region and surrounding a second portion of the sidewalls of the second portion of the one or more vertical fins;
the interfacial layer disposed on a third portion of the sidewalls of the second portion of the one or more vertical fins;
a gate stack disposed over a top surface of the bottom spacer and on the interfacial layer;
a gate encapsulation layer disposed over the gate stack;
the top spacer comprising: (i) a first portion disposed on sidewalls of the first portion of the one or more vertical fins; and (ii) a second portion filling a divot between the gate encapsulation layer and the gate stack;
top source/drain regions disposed over top surfaces of the one or more vertical fins;
top contacts disposed over the top source/drain regions; and
an interlayer dielectric disposed over the gate encapsulation layer and surrounding the top contacts.

### Claim 11

An integrated circuit comprising:
a vertical transport field-effect transistor structure comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first portion proximate top surfaces thereof and a second portion below the first portion;
top spacers disposed on sidewalls of the first portion of the one or more vertical fins; and
an interfacial layer disposed on sidewalls of the second portion of the one or more vertical fins;
wherein the one or more vertical fins provide vertical transport channels for one or more vertical transport field-effect transistors.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first top spacers protect the interfacial layer such that the interfacial layer has a uniform thickness.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, further comprising a gate stack disposed over the interfacial layer.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, wherein the gate stack comprises:
a gate dielectric layer having an inverted-L shape profile proximate the top surface of the one or more vertical fins; and
a gate conductor layer having an inverted-L shape profile below the inverted-L shape profile of the gate dielectric layer, a top surface of the gate conductor layer being below a top surface of the gate dielectric layer.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the inverted-L shape profile of the gate dielectric layer comprises:
a first vertically oriented portion adjacent sidewalls of the interfacial layer; and
a first horizontally oriented portion extending from an upper portion of the first vertically oriented portion below a bottom surface of the top spacer.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the inverted-L shape profile of the gate conductor layer comprises:
a second vertically oriented portion adjacent sidewalls of the first vertically oriented portion of the gate dielectric layer; and
a second horizontally oriented portion extending from an upper portion of the second vertically oriented portion of the gate conductor layer below a bottom surface of the first horizontally oriented portion of the gate dielectric layer.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein at least a portion of a top surface of the second horizontally oriented portion of the gate conductor layer is exposed by the first horizontally oriented portion of the gate dielectric layer.

### Claim 18 (depends on 14)

The integrated circuit of claim 14, further comprising a gate encapsulation layer surrounding at least a first portion of the gate conductor layer.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the top spacer comprises spacer material in a divot space defined between the gate encapsulation layer and a second portion of the gate conductor layer.

### Claim 20 (depends on 11)

The integrated circuit of claim 11, further comprising:
a bottom source/drain region disposed over the top surface of the substrate and surrounding a first portion of the sidewalls of the second portion of the one or more vertical fins;
a bottom spacer disposed over a top surface of the bottom source/drain region and surrounding a second portion of the sidewalls of the second portion of the one or more vertical fins;
the interfacial layer disposed on a third portion of the sidewalls of the second portion of the one or more vertical fins;
a gate stack disposed over a top surface of the bottom spacer and on the interfacial layer;
a gate encapsulation layer disposed over the gate stack;
the top spacer comprising: (i) a first portion disposed on sidewalls of the first portion of the one or more vertical fins; and (ii) a second portion filling a divot between the gate encapsulation layer and the gate stack;
top source/drain regions disposed over top surfaces of the one or more vertical fins;
top contacts disposed over the top source/drain regions; and
an interlayer dielectric disposed over the gate encapsulation layer and surrounding the top contacts.