# US 2022/0045191 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045191 A1 - Document ID: US20220045191A1 - Status: Published application - Kind: A1 - Application number: 17/409,293 - Filed: 2021-08-23 - Published: 2022-02-10 - Earliest claimed: 2018-01-30 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Yuzo FUKUZAKI - Web page: https://patentgrep.com/patent/US20220045191A1 ## CPC - H10D 62/121: {oriented parallel to substrates} - H10D 64/681: {having a compositional variation, e.g. multilayered} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 64/519: {characterised by their top-view geometrical layouts} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N≥3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion. ## Claims ### Claim at position 1 -7. (canceled) ### Claim 8 A semiconductor device, comprising: a stacked structure having a channel formation region layer and a gate electrode layer alternately arranged on top of each other on a base, wherein a lowermost layer of the stacked structure is formed with a 1st layer of the gate electrode layers, wherein an uppermost layer of the stacked structure is formed with an Nth (where N≥3) layer of the gate electrode layers, and wherein each channel formation region layer includes at least one channel structure portion and each channel structure portion includes extensions provided on each end of the at least one channel structure portion. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the at least one channel structure portion has a nanosheet structure or a nanowire structure. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein a second end face of each of the channel formation region layers has the at least one channel structure portion connected to one of source/drain regions common to the channel formation region layers, and wherein a fourth end face of each of the channel formation region layers has the at least one channel structure portion connected to the other of the source/drain regions common to the channel formation region layers. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein a second end face of each of the gate electrode layers is opposed to one of the source/drain regions via a first insulating film, and wherein a fourth end face of each of the gate electrode layers is opposed to the other of the source/drain regions via a second insulating film. ### Claim 12 (depends on 8) The semiconductor device according to claim 8, wherein the at least one channel structure portion includes two channel structure portions. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the at least one channel structure portion has a nanosheet structure. ### Claim 14 (depends on 8) The semiconductor device according to claim 8, wherein the at least one channel structure portion includes three channel structure portions. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the at least one channel structure portion has a nanowire structure. ### Claim 16 (depends on 8) The semiconductor device according to claim 8, wherein a first end face of an odd-numbered layer of the gate electrode layers protrudes from a first end face of the channel formation region layer, and wherein a third end face of an even-numbered layer of the gate electrode layers protrudes from a third end face of the channel formation region layer. ### Claim 17 (depends on 8) The semiconductor device according to claim 8, wherein a High-k material insulating film is provided between each of the channel formation region layers and the gate electrode layers. ### Claim 18 (depends on 11) The semiconductor device according to claim 11, wherein a High-k material insulating film is provided between each of the channel formation region layers and the gate electrode layers and extends across the first and second insulating films. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, wherein the High-k material insulating film extends across the extensions. ### Claim 20 (depends on 8) The semiconductor device according to claim 8, wherein the at least one channel structure portion includes Si, SiGe, Ge or InGaAs. ### Claim 21 (depends on 8) The semiconductor device according to claim 8, wherein each of the gate electrode layers includes TiN, TaN, Al, or W. ### Claim 22 (depends on 9) The semiconductor device according to claim 9, wherein both ends of a wire of the nanowire structure has a diameter of 5 nm to 10 nm. ### Claim 23 A method for manufacturing a semiconductor device, comprising: forming a stacked structure having a channel formation region layer and a gate electrode layer alternately arranged on top of each other on a base; forming a lowermost layer of the stacked structure with a 1st layer of the gate electrode layers; and forming an uppermost layer of the stacked structure with an Nth (where N≥3) layer of the gate electrode layers, wherein each channel formation region layer includes at least one channel structure portion and each channel structure portion includes extensions provided on each end of the at least one channel structure portion. ### Claim 24 (depends on 23) The method according to claim 23, wherein the at least one channel structure portion has a nanosheet structure or a nanowire structure. ### Claim 25 (depends on 23) The method according to claim 23, wherein a second end face of each of the channel formation region layers has the at least one channel structure portion connected to one of source/drain regions common to the channel formation region layers, and wherein a fourth end face of each of the channel formation region layers has the at least one channel structure portion connected to the other of the source/drain regions common to the channel formation region layers. ### Claim 26 (depends on 25) The method according to claim 25, wherein a second end face of each of the gate electrode layers is opposed to one of the source/drain regions via a first insulating film, and wherein a fourth end face of each of the gate electrode layers is opposed to the other of the source/drain regions via a second insulating film. ### Claim 27 (depends on 23) The method according to claim 23, wherein a first end face of an odd-numbered layer of the gate electrode layers protrudes from a first end face of the channel formation region layer, and wherein a third end face of an even-numbered layer of the gate electrode layers protrudes from a third end face of the channel formation region layer.