# US 2022/0045181 A1 · Semiconductor device and method of forming same

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- Number: US 2022/0045181 A1
- Document ID: US20220045181A1
- Status: Published application
- Kind: A1
- Application number: 17/116,703
- Filed: 2020-12-09
- Published: 2022-02-10
- Earliest claimed: 2020-08-07
- Assignees: Semiconductor Manufacturing Electronics (Shaoxing) Corporation
- Applicants: Semiconductor Manufacturing Electronics (ShaoXing) Corporation
- Inventors: Jinxing SONG; Maojie CONG; Jiagui YUAN
- Web page: https://patentgrep.com/patent/US20220045181A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 64/20: Electrodes characterised by their shapes, relative sizes or dispositions
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device and a method of forming the device are disclosed. In the semiconductor device, a shielded gate trench field effect transistor (FET) is formed in a cell region, and a super barrier rectifier (SBR) is formed in a non-cell region. In the SBR, a second dielectric layer has an upper dielectric layer and a lower dielectric layer, which are joined to each other smoothly by virtue of a beak-like portion. This avoids the presence of any sharp corner between the upper and lower dielectric layers and effectively mitigates the problem of an excessively small thickness of the upper dielectric layer at a bottom portion thereof, which tends to cause current leakage.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate defining a cell region and a non-cell region, the non-cell region comprising a source-connecting region;
a shielded gate trench field effect transistor (FET) formed in the cell region, the shielded gate trench FET comprising: a first trench formed in the substrate; a first dielectric layer covering both a bottom and a sidewall of the first trench; and a shield electrode, a separation layer and a first gate electrode, which are sequentially stacked in the first trench; and
a super barrier rectifier (SBR) formed in the non-cell region, the SBR comprising: a second trench formed in the substrate; a second dielectric layer covering both a bottom and a sidewall of the second trench, the second dielectric layer comprising a second lower dielectric layer and a second upper dielectric layer residing on and joined to the second lower dielectric layer, the second upper dielectric layer having a thickness smaller than a thickness of the second lower dielectric layer, the second lower dielectric layer having a beak-like portion proximal to and tapered in thickness toward the second upper dielectric layer, the second upper dielectric layer smoothly joined to the beak-like portion of the second lower dielectric layer, the thickness of the second upper dielectric layer further being smaller than a portion of the first dielectric layer that vertically corresponds to the first gate electrode; and a second gate electrode being an integral structure filling up a bottom portion of the second trench, with a top surface of the second gate electrode being above the shield electrode, both the second gate electrode and the shield electrode being electrically picked up by the source-connecting region,
wherein the semiconductor device further comprises a well region formed in the substrate beside the first trench and having a lateral overlap with the first gate electrode, the well region further extending to the substrate beside the second trench and having a lateral overlap with the second gate electrode, the thickness of the second upper dielectric layer is between 40 Å and 100 Å adjustable according to a concentration of dopant ions in the well region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the non-cell region further comprises a rectifier region,
wherein the SBR is formed in the rectifier region, and
wherein a source-connecting structure is formed in the source-connecting region, the source-connecting structure comprising: a third trench formed in the substrate; a third dielectric layer covering both a bottom and a sidewall of the third trench; and a connecting electrode filling up the third trench, the connecting electrode connecting to the shield electrode for electrically picking up the shield electrode.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the substrate defines a plurality of cell regions and at least one rectifier region, wherein the first trenches of the plurality of cell regions all extend in a predetermined direction, the second trench in each of the at least one rectifier region interposed between adjacent first trenches, and wherein the first trenches all extend to the third trench at ends thereof to communicate with the third trench.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a source-connecting structure is formed in the source-connecting region, the source-connecting structure comprising:
a third trench formed in the substrate, wherein at least part of the third trench constitutes the second trench of the SBR and is defined as a function-integrated region;
a third dielectric layer covering both a bottom and a sidewall of the third trench, wherein a portion of the third dielectric layer formed within the function-integrated region constitutes the second dielectric layer of the SBR; and
a connecting electrode filling up the third trench, the connecting electrode electrically connecting the shield electrode, wherein a portion of the connecting electrode formed within the function-integrated region constitutes the second gate electrode of the SBR.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the substrate defines a plurality of cell regions, wherein the first trenches of the plurality of cell regions all extend in a predetermined direction, and wherein the first trenches all extend to the second trench at ends thereof to communicate with the second trench.

### Claim 6

(canceled)

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises a first lower dielectric layer and a first upper dielectric layer residing on and joined to the first lower dielectric layer, the first lower dielectric layer covering both the bottom of the first trench and a portion of the sidewall of the first trench that corresponds to the shield electrode, the first upper dielectric layer covering at least a portion of the sidewall of the first trench that corresponds to the first gate electrode.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first lower dielectric layer has a beak-like portion proximal to and tapered in thickness toward the first upper dielectric layer, and wherein the beak-like portion of the first lower dielectric layer is located at a height that is equal to a height where the beak-like portion of the second lower dielectric layer is located.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first trench and the second trench are equal in depth.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a source region formed in the substrate beside the first trench and having a lateral overlap with the first gate electrode, the source region further extending to the substrate beside the second trench and having a lateral overlap with the second gate electrode.

### Claim 11

A method of forming a semiconductor device, comprising:
providing a substrate defining a cell region and a non-cell region;
forming a plurality of trenches in the substrate, the plurality of trenches including a first trench in the cell region and a second trench in the non-cell region;
forming a lower dielectric layer covering both a bottom and a lower portion of a sidewall of each of the plurality of trenches, wherein forming the lower dielectric layer comprises forming a first lower dielectric layer in the first trench and a second lower dielectric layer in the second trench so that at least an end portion of the second lower dielectric layer is a beak-like portion with a gradually reduced thickness;
forming an upper dielectric layer covering an upper portion of the sidewall of each of the plurality of trenches, wherein forming the upper dielectric layer comprises forming a sacrificial dielectric layer on the upper portion of the sidewall of the first trench and a second upper dielectric layer on the upper portion of the sidewall of the second trench, the second upper dielectric layer having a thickness smaller than a thickness of the second lower dielectric layer, the second upper dielectric layer smoothly joined to the beak-like portion of the second lower dielectric layer; and
forming electrodes in the plurality of trenches, wherein forming the electrodes comprises: forming a shield electrode in a bottom portion of the first trench and a second gate electrode in the second trench, the second gate electrode being an integral structure filling up a bottom portion of the second trench and having a top surface above the shield electrode; and successively forming, above the shield electrode, a separation layer, a first upper dielectric layer and a first gate electrode in the first trench, the first upper dielectric layer having a thickness greater than a thickness of the second upper dielectric layer,
the method further comprising forming a well region, the well region being formed in the substrate beside the first trench and having a lateral overlap with the first gate electrode, the well region further extending to the substrate beside the second trench and having a lateral overlap with the second gate electrode,
wherein the thickness of the second upper dielectric layer is between 40 Å and 100 Å adjustable according to a concentration of dopant ions in the well region.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the plurality of trenches in the substrate comprises:
forming a mask layer on a top surface of the substrate and etching the substrate using the mask layer, so that a first upper trench is formed in the substrate in the cell region and a second upper trench is formed in the substrate in the non-cell region;
successively forming a silicon oxide layer and a silicon nitride layer over a sidewall of each of the first and second upper trenches, with a bottom of each of the first and second upper trenches being exposed; and
etching the bottoms of the first and second upper trenches with the silicon nitride layers serving as masks so that the bottoms of the first and second upper trenches extend downward to form the first and the second trenches.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the lower dielectric layer covering both the bottom and the lower portion of the sidewall of each of the plurality of trenches comprises:
performing a local oxidation process with the silicon oxide layer and the silicon nitride layer together serving as a mask, thereby forming the first lower dielectric layer having a beak-like portion in the first trench and the second lower dielectric layer having a beak-like portion in the second trench.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the upper dielectric layer covering the upper portion of the sidewall of each of the plurality of trenches comprises:
removing the silicon oxide layer and the silicon nitride layer, exposing the upper portion of the sidewall of each of the first and second trenches above the lower dielectric layer; and
performing a first oxidation process, thereby forming the sacrificial dielectric layer on the upper portion of the sidewall of the first trench and the second upper dielectric layer on the upper portion of the sidewall of the second trench.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the electrodes in the plurality of trenches comprises:
filling each of the plurality of trenches with an electrode material layer, wherein a portion of the electrode material layer in the second trench forms the second gate electrode that covers the second upper dielectric layer;
removing a portion of the electrode material layer in the first trench so that a remaining portion of the electrode material layer on the bottom of the first trench forms the shield electrode and the sacrificial dielectric layer in the first trench is exposed;
forming the separation layer in the first trench to cover the shield electrode and removing the sacrificial dielectric layer, thereby exposing the upper portion of the sidewall of the first trench; and
forming the first upper dielectric layer in the first trench by performing a second oxidation process and forming the first gate electrode in the first trench.

### Claim 16 (depends on 11)

The method of claim 11, further comprising forming a source region, the source region and the well region both formed in the substrate beside the first trench and thereby forming a shielded gate trench field effect transistor (FET) in the cell region, the well region and the source region also both formed in the substrate beside the second trench and thereby forming a super barrier rectifier (SBR) in the non-cell region.