# US 2022/0045170 A1 · Semiconductor device and method for fabricating the same

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- Number: US 2022/0045170 A1
- Document ID: US20220045170A1
- Status: Published application
- Kind: A1
- Application number: 17/509,061
- Filed: 2021-10-24
- Published: 2022-02-10
- Earliest claimed: 2016-08-10
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chih-Kai Hsu; Ssu-I Fu; Yu-Hsiang Hung; Wei-Chi Cheng; Jyh-Shyang Jenq
- Web page: https://patentgrep.com/patent/US20220045170A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

## Claims

### Claim 1

A method for fabricating semiconductor device, comprising:
forming a gate structure on a substrate;
forming a spacer around the gate structure; and
forming a buffer layer adjacent to the gate structure, wherein the buffer layer comprises a crescent moon shape and the buffer layer comprises an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, wherein the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the buffer layer comprises a first width and a second width directly under the spacer, wherein the second width is greater than the first width.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first width is between 3 nm to 7 nm.

### Claim 4 (depends on 2)

The method of claim 2, wherein the second width is between 5 nm to 9 nm.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a recess adjacent to the spacer;
forming the buffer layer in the recess; and
forming an epitaxial layer on the buffer layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein a bottom surface of the epitaxial layer comprises a curve.

### Claim 7 (depends on 6)

The method of claim 6, wherein the buffer layer comprises a vertical thickness directly under a valley point of the curve.

### Claim 8 (depends on 7)

The method of claim 7, wherein the vertical thickness is between 7 nm to 11 nm.

### Claim 9 (depends on 5)

The method of claim 5, wherein a top surface of the epitaxial layer is even with a top surface of the substrate.

### Claim 10 (depends on 1)

The method of claim 1, wherein an etching to deposition ratio of the buffer layer is between 0.2 to 0.5.