# US 2022/0045167 A1 · Vfet standard cell architecture with improved contact and super via > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045167 A1 - Document ID: US20220045167A1 - Status: Published application - Kind: A1 - Application number: 17/510,753 - Filed: 2021-10-26 - Published: 2022-02-10 - Earliest claimed: 2019-03-15 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jung Ho DO; Rwik SENGUPTA - Web page: https://patentgrep.com/patent/US20220045167A1 ## CPC - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/252: {for vertical or pseudo-vertical devices} - H10W 20/42: Vias, e.g. via plugs - H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0195: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 89/10: Integrated device layouts - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit. ## Claims ### Claim 1 A cell architecture comprising: 1st-type top source/drain (S/D) contact structures respectively formed on top S/D regions of at least two of vertical field-effect transistors (VFETs) constituting a logic circuit, respectively; at least one gate contact structure connected to at least one gate connection pattern connecting gates of the two of the VFETs to each other; 1st metal patterns extended in a Y-direction and configured to receive one or more input signals of the logic circuit, and transmit out an output signal of the logic circuit; and 2nd metal patterns extended in an X-direction and provided for internal routing of the logic circuit by connecting at least two of the 1st-type top S/D contact structures to one of the 1st metal patterns to transmit out the output signal, wherein the two of the 1st-type top S/D contact structures have a substantially-square shape in a plan view of the cell architecture, and wherein the 1st metal patterns are formed at a higher level than the 2nd metal patterns which are formed at a higher level than the 1st-type top S/D contact structures. ### Claim 2 (depends on 1) The cell architecture of claim 1, further comprising at least two 1st vias respectively formed on the 2nd metal patterns to connect the two of the 1st-type top S/D contact structures to the one of the 1st metal patterns. ### Claim 3 (depends on 2) The cell architecture of claim 2, further comprising at least one super via formed on the gate contact structure and connected to another one of the 1st metal patterns to receive one of the input signals. ### Claim 4 (depends on 3) The cell architecture of claim 3, further comprising at least two 2nd vias respectively formed on the two of the 1st-type top S/D contact structures, and connected to the 2nd metal patterns. ### Claim 5 (depends on 3) The cell architecture of claim 3, wherein the two of the 1st-type top S/D contact structures are connected to the 2nd metal patterns without through respective vias. ### Claim 6 (depends on 2) The cell architecture of claim 2, wherein the gate contact structure is connected to another one of the 1st metal patterns to receive one of the input signals without through a via. ### Claim 7 (depends on 1) The cell architecture of claim 1 further comprising 2nd-type top S/D contact structures having a bar shape in the plan view of the cell architecture, formed on top S/D regions of another at least two of the VFETs, and extended to an edge of the cell architecture to be connected to a power rail and a ground rail, wherein upper surfaces of the 2nd-type top S/D contact structures are spaced apart from lower surfaces of the 2nd metal patterns. ### Claim 8 A cell architecture comprising: top source/drain (S/D) contact structures respectively formed on top S/D regions of at least two of vertical field-effect transistors (VFETs) constituting a logic circuit, respectively; at least one gate contact structure connected to at least one gate connection pattern connecting gates of the two of the VFETs to each other; 1st metal patterns extended in a Y-direction and configured to receive one or more input signals of the logic circuit and transmit out an output signal of the logic circuit; 2nd metal patterns extended in an X-direction and provided for internal routing of the logic circuit by connecting at least two of the top S/D contact structures to one of the 1st metal patterns to transmit out the output signal; and at least one super via formed on the gate contact structure and connected to another one of the 1st metal patterns to receive one of the input signals, wherein the 1st metal patterns are formed at a higher level than the 2nd metal patterns which are formed at a higher level than the top S/D contact structures. ### Claim 9 (depends on 8) The cell architecture of claim 8, wherein the top S/D contact structures have a substantially-square shape in a plan view of the cell architecture. ### Claim 10 (depends on 9) The cell architecture of claim 9, further comprising top S/D contact structures respectively formed on top S/D regions of another at least two of the VFETs, extended to an edge of the cell architecture to be connected to a power rail or a ground rail, and having upper surfaces thereof spaced apart from a lower surface of the 2nd metal pattern.