# US 2022/0045166 A1 · Semiconductor device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045166 A1 - Document ID: US20220045166A1 - Status: Published application - Kind: A1 - Application number: 17/508,197 - Filed: 2021-10-22 - Published: 2022-02-10 - Earliest claimed: 2016-09-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jung Gil YANG; Dong Il BAE; Chang Woo SOHN; Seung Min SONG; Dong Hun LEE - Web page: https://patentgrep.com/patent/US20220045166A1 ## CPC - H10D 62/121: {oriented parallel to substrates} - H10D 30/503: {having non-rectangular cross-sections} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0158: {the components including FinFETs} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors} - H10D 84/834: {comprising FinFETs} - H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 84/853: {comprising FinFETs} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D 89/10: Integrated device layouts - H10D 84/0142: {the gate conductors having different shapes or dimensions} - H10D 84/0179: {the gate conductors having different shapes or dimensions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern. ## Claims ### Claim 1 A method for fabricating a semiconductor device, comprising: providing a substrate including a first region and a second region, forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternately stacked on the substrate, forming a blocking film covering the first region and exposing the second region, performing an ion implantation on the second region to lower an etch selectivity of the first semiconductor pattern on the second region, forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern, forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode, and etching the first semiconductor pattern, wherein the first semiconductor pattern on the first region is completely removed, and the first semiconductor pattern on the second region remains to form a supporting pattern. ### Claim 2 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein the etching the first semiconductor pattern includes: etching a portion of the second semiconductor pattern on the first region and a portion of the second semiconductor pattern on the second region. ### Claim 3 (depends on 2) The method for fabricating the semiconductor device of claim 2, wherein the etched portion of the second semiconductor pattern on the first region is an end portion of the second semiconductor pattern on the first region, and the etched portion of the second semiconductor pattern on the second region is an end portion of the second semiconductor pattern on the second region. ### Claim 4 (depends on 2) The method for fabricating the semiconductor device of claim 2, wherein the portion of the second semiconductor pattern on the second region is etched to a greater extent than the portion of the first semiconductor pattern on the second region. ### Claim 5 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein an end portion of the first semiconductor pattern is etched to a greater extent than a center portion of the first semiconductor pattern. ### Claim 6 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein the first semiconductor pattern on the second region is disposed on the upper most portion of the second fin-type pattern. ### Claim 7 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein the first semiconductor pattern includes SiGe. ### Claim 8 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein the second semiconductor pattern includes Si, and an impurity concentration of the second semiconductor on the second region is different from than the impurity concentration of the second semiconductor on the first region. ### Claim 9 A method for fabricating a semiconductor device, comprising: providing a substrate including a first region and a second region, forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternatively stacked on the substrate, performing an ion implantation on the second region except on the first region, wherein an impurity concentration of the second semiconductor pattern on the second region is higher than the impurity concentration of the second semiconductor pattern on the first region, forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern, forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode, forming a first source/drain on a side of the first dummy gate electrode and a second source/drain on a side of the second dummy gate electrode, removing the first dummy gate electrode and the second dummy gate electrode, and removing completely the first semiconductor pattern on the first region and a portion of the first semiconductor pattern on the second region, wherein the first semiconductor pattern on the second region remains to form a supporting pattern. ### Claim 10 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein the first semiconductor pattern has a material different from the second semiconductor pattern. ### Claim 11 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein a side surface of the supporting pattern is concave inward. ### Claim 12 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein a side surface of the second semiconductor pattern in second region is convex outward. ### Claim 13 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein the supporting pattern includes the same impurity as the second semiconductor pattern on the second region. ### Claim 14 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein the first spacer includes a first outer spacer and a first inner spacer, wherein the second spacer includes a second outer spacer and a second inner spacer, and wherein the forming the first spacer on the side wall of the first dummy gate electrode and the second spacer on the side wall of the second dummy gate electrode includes: forming the first outer spacer on the side wall of the first dummy gate electrode and the second outer spacer on the side wall of the second dummy gate electrode, etching at least of the second semiconductor pattern on the first region to form a first dimple between the first outer spacer, and at least of the second semiconductor pattern on the second region to form a second dimple between the second outer spacer, and forming the first inner spacer filing the first dimple and the second inner spacer filing the second dimple. ### Claim 15 (depends on 14) The method for fabricating the semiconductor device of claim 14, further comprising: forming a first gate electrode surrounding the second semiconductor pattern on the first region and a second gate electrode intersecting the second fin-type structure, wherein the first inner spacer is disposed on a side wall of the first gate electrode, and the second inner spacer is disposed on a side wall of the supporting pattern. ### Claim 16 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein the first region is an NMOS region, and the second region is a PMOS region. ### Claim 17 (depends on 9) The method for fabricating the semiconductor device of claim 9, wherein the first region is an active region, and the second region is a dummy region. ### Claim 18 A method for fabricating a semiconductor device, comprising: providing a substrate including a first region and a second region, forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternately stacked on the substrate, forming a blocking film covering the first region and exposing the second region, performing an ion implantation on the second region to lower an etch selectivity of the first semiconductor pattern on the second region, removing the blocking film, forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern, forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode, forming a first source/drain on a side of the first dummy gate electrode and a second source/drain on a side of the second dummy gate electrode, removing the first dummy gate electrode and the second dummy gate electrode, and etching the first semiconductor pattern, wherein the first semiconductor pattern on the first region is completely removed, and the first semiconductor pattern on the second region remains to form a supporting pattern, and wherein a width of the first semiconductor pattern on the second region is greater than a width of the second semiconductor pattern on the second region, forming a first gate insulating layer on the second semiconductor pattern on the first region and a second gate insulating layer on the first semiconductor pattern and the second semiconductor pattern on the second region, and forming a first gate electrode on the first gate insulating layer and a second gate electrode on the second gate insulating layer. ### Claim 19 (depends on 18) The method for fabricating the semiconductor device of claim 18, wherein a side wall of the first semiconductor pattern and second semiconductor pattern on the second region has a rugged shape. ### Claim 20 (depends on 18) The method for fabricating the semiconductor device of claim 18, wherein an impurity concentration of the second semiconductor on the second region is higher than the impurity concentration of the second semiconductor on the first region.