# US 2022/0045162 A1 · Interposer structure and method for manufacturing thereof

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- Number: US 2022/0045162 A1
- Document ID: US20220045162A1
- Status: Published application
- Kind: A1
- Application number: 17/511,190
- Filed: 2021-10-26
- Published: 2022-02-10
- Earliest claimed: 2019-10-28
- Assignees: AP Memory Technology Corp.
- Applicants: Ap Memory Technology Corporation
- Inventors: WENLIANG CHEN
- Web page: https://patentgrep.com/patent/US20220045162A1

## CPC

- H10D 1/716: {having vertical extensions}
- H01G 2/06: specially adapted for mounting on a printed-circuit support
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/228: Terminals
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H01G 4/385: {Single unit multiple capacitors, e.g. dual capacitor in one coil}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 84/212: {of only capacitors}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/496: {Capacitor integral with wiring layers}
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An interposer structure is provided. The interposer structure includes a plurality of interposer units in an array arrangement from a top view perspective. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the plurality of second regions is free of the capacitor structure. The first region surrounds the plurality of second regions. A method for manufacturing an interposer structure is also provided.

## Claims

### Claim 1

An interposer structure, comprising:
a substrate portion;
a wiring portion over the substrate portion;
an interconnect portion over the wiring portion;
a through via penetrating the substrate portion and the wiring portion; and
a capacitor structure embedded in the wiring portion;
wherein the interconnect portion comprises a first metal wire electrically coupled to the capacitor structure.

### Claim 2 (depends on 1)

The interposer structure of claim 1, wherein the first metal wire is disposed over the through via, and the first metal wire is electrically coupled to the through via and the capacitor structure.

### Claim 3 (depends on 1)

The interposer structure of claim 1, wherein the through via penetrates the substrate portion, the wiring portion, and the interconnect portion, and the through via is disconnected from the first metal wire.

### Claim 4 (depends on 1)

The interposer structure of claim 1, wherein the interconnect portion is configured to bond with a first semiconductor die, and the substrate portion is configured to bond with a package substrate.

### Claim 5 (depends on 4)

The interposer structure of claim 4, wherein the interconnect portion is further configured to bond with a second semiconductor die, the interconnect portion further comprises a second metal wire electrically connected to the first semiconductor die and the second semiconductor die.

### Claim 6 (depends on 5)

The interposer structure of claim 5, wherein the second metal wire is disconnected from the first metal wire or the through via.

### Claim 7 (depends on 1)

The interposer structure of claim 1, wherein the substrate portion is composed of semiconductor or insulator.

### Claim 8 (depends on 1)

The interposer structure of claim 1, wherein each of the capacitor structures comprises:
a bottom metal plate;
a top metal plate over the bottom metal plate; and
a plurality of capacitor cells between the bottom metal plate and the top metal plate.

### Claim 9 (depends on 8)

The interposer structure of claim 8, wherein each of the capacitor cells comprises:
a first conductor film, comprising:
a first portion connected to the bottom metal plate; and
a second portion connected to the first portion and extending toward the top metal plate from the bottom metal plate; and
a second conductor film adjacent to the first conductor film and connected to the top metal plate and extending toward the bottom metal plate from the top metal plate;
wherein the second conductor film is vertically interleaving with the second portion of the first conductor film.

### Claim 10 (depends on 8)

The interposer structure of claim 8, further comprising:
a first contact connecting a first metal layer of the interconnect portion and the top metal plate; and
a second contact connecting the first metal layer and the bottom metal plate;
wherein the first contact and the second contact are substantially identical in vertical lengths.

### Claim 11 (depends on 8)

The interposer structure of claim 8, further comprising:
a first contact connecting a first metal layer of the interconnect portion and the top metal plate; and
a second contact connecting the first metal layer and the bottom metal plate;
wherein the first contact and the second contact are different in vertical lengths.

### Claim 12 (depends on 8)

The interposer structure of claim 8, wherein a distance between the bottom metal plate and the top metal plate is in a range of from about 1 μm to about 2 μm.

### Claim 13 (depends on 1)

The interposer structure of claim 1, further comprising:
a memory structure in the wiring portion.

### Claim 14

An interposer structure, comprising:
a plurality of interposer units in an array arrangement from a top view perspective, each comprising:
a first region having a capacitor structure; and
a plurality of second regions, each being free of the capacitor structure, the first region surrounding the plurality of second regions.

### Claim 15 (depends on 14)

The interposer structure of claim 14, wherein adjacent interposer units are spaced apart by a scribe line.

### Claim 16 (depends on 14)

The interposer structure of claim 14, wherein an area ratio of the first region in one of the interposer units is in a range of from about 50% to about 80%.

### Claim 17 (depends on 14)

The interposer structure of claim 14, wherein a pitch between adjacent second regions is less than about 100 μm, and a length on a side of one of the interposer units is in a range of from about 0.5 to 1 mm.

### Claim 18 (depends on 14)

The interposer structure of claim 14, wherein the second region in each of the interposer units is configured to accommodate a through via penetrating the interposer structure.

### Claim 19 (depends on 14)

The interposer structure of claim 14, wherein a height of the capacitor structure is in a range of from about 1 μm to about 2 μm and the capacitor structure is located between a substrate portion and an interconnect portion of the interposer structure from a cross sectional view perspective.

### Claim 20

A method for manufacturing an interposer structure, the method comprising:
forming a wiring portion over a front side of a substrate portion; and
forming a capacitor structure within the wiring portion during forming the wiring portion;
wherein the capacitor structures are formed by a DRAM process.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
forming a through via penetrating the wiring portion and extending toward the substrate portion, wherein the through via is free from overlapping with the capacitor structure;
forming an interconnect portion over the wiring portion, wherein a first metal layer of the interconnect portion is electrically coupled to the capacitor structure and the through via; and
thinning down the substrate portion from a back side of the substrate portion to expose an end of the through via.

### Claim 22 (depends on 20)

The method of claim 20, wherein forming the capacitor structure within the wiring portion comprises:
forming a plurality of capacitor electrode structures coupled to the capacitor structure;
wherein the plurality of capacitor electrode structures comprise a coplanar top surface.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
forming a plurality of metal contacts extending from a top surface of the wiring portion to connect to the capacitor electrode structures; and
forming an interconnecting portion over the wiring portion.

### Claim 24 (depends on 20)

The method of claim 20, wherein a height of the capacitor structure is in a range of from about 1 μm to about 2 μm.