# US 2022/0045153 A1 · Display panel, preparing method thereof, and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045153 A1 - Document ID: US20220045153A1 - Status: Published application - Kind: A1 - Application number: 16/758,533 - Filed: 2020-03-10 - Published: 2022-02-10 - Earliest claimed: 2020-03-10 - Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd. - Inventors: Jia TANG - Web page: https://patentgrep.com/patent/US20220045153A1 ## CPC - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6723: {having light shields} - H10D 30/6729: {characterised by the electrodes} - H10D 86/60: wherein the TFTs are in active matrices - H10K 59/1216: {the pixel elements being capacitors} - H10K 59/122: Pixel-defining structures or layers, e.g. banks - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10K 59/126: Shielding, e.g. light-blocking means over the TFTs - H10K 59/873: {Encapsulations} - H10K 71/00: Manufacture or treatment specially adapted for the organic devices covered by this subclass - H10K 59/1213: {the pixel elements being TFTs} - H10K 2102/103: {comprising indium oxides, e.g. ITO} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A display panel, a method for preparing a display panel, and a display device are disclosed. The display panel includes a substrate layer; a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer; an active layer and a second electrode plate of the storage capacitor on the buffer layer; a gate insulating layer on the buffer layer and the active layer, and a source, a gate and a drain on the gate insulating layer. ## Claims ### Claim 1 A display panel comprising: a substrate layer; a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer; an active layer and a second electrode plate of the storage capacitor on the buffer layer; a gate insulating layer on the buffer layer and the active layer, and, a source, a gate and a drain on the gate insulating layer; wherein the source is connected to the light shielding metal layer through a first via hole; a second via hole and a third via hole are defined by the gate insulating layer, the source is connected to one side of the active layer through the second via hole, and the drain is connected to other side of the active layer through the third via hole; wherein widths of the source and the drain are both smaller than a width of the active layer, a range of a vertical distance between an edge of a projection of the source projected on the active layer and an edge of a projection of the second via hole projected on the active layer is greater than 0 and less than or equal to 2 microns, a range of a vertical distance between an edge of a projection of the drain projected on the active layer and an edge of a projection of the third via hole projected on the active layer is greater than 0 and less than or equal to 2 microns. ### Claim 2 (depends on 1) The display panel as claimed in claim 1, wherein material of the active layer is indium gallium zinc oxide. ### Claim 3 (depends on 1) The display panel as claimed in claim 1, wherein material of the first electrode plate is same as material of the light-shielding metal layer. ### Claim 4 (depends on 1) The display panel as claimed in claim 1, wherein material of the first electrode plate is indium tin oxide. ### Claim 5 (depends on 1) The display panel as claimed in claim 1, wherein material of the second electrode plate is same as material of the source, the gate, or the drain. ### Claim 6 (depends on 1) The display panel as claimed in claim 1, further comprising a passivation layer located on the buffer layer and covering the second electrode plate, the source, the gate, and the drain; a color resist layer located on the passivation layer and corresponding to a light transmitting region of the display panel; a protective layer located on the passivation layer and covering the color resist layer; a pixel electrode layer located on the protective layer; and a pixel definition layer located on the protective layer and the pixel electrode layer, wherein the pixel electrode layer is connected to the source through a fourth via hole. ### Claim 7 (depends on 6) The display panel as claimed in claim 6, further comprising: an organic light emitting layer located on the pixel electrode layer; and a common electrode layer located on the organic light emitting layer and the pixel definition layer. ### Claim 8 (depends on 6) The display panel as claimed in claim 6, wherein material of the pixel definition layer is a hydrophobic material. ### Claim 9 (depends on 6) The display panel as claimed in claim 6, wherein material of the pixel definition layer is a non-hydrophobic material. ### Claim 10 A method for preparing a display panel, comprising steps of: provide a substrate layer; preparing a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; preparing a buffer layer on the substrate layer, wherein the buffer layer covers the light shielding metal layer and the first electrode plate; preparing an active layer and a second electrode plate of the storage capacitor on the buffer layer; preparing a gate insulating layer on the buffer layer, wherein the gate insulating layer covers the active layer and the second electrode plate; etching the gate insulating layer and the buffer layer to form a first via hole, a second via hole, and a third via hole, respectively; conducting a first conductorization of regions of the active layer corresponding to the second via hole and the third via hole; preparing a source, a gate, and a drain on the gate insulating layer, wherein the source is connected to the light shielding metal layer through the first via hole; the source is connected to one side of the active layer through the second via hole, and the drain is connected to other side of the active layer through the third via hole; wherein widths of the source and the drain are both smaller than a width of the active layer, wherein a range of a vertical distance between an edge of a projection of the source projected on the active layer and an edge of a projection of the second via hole projected on the active layer is greater than 0 and less than or equal to 2 microns, a range of a vertical distance between an edge of a projection of the drain projected on the active layer and an edge of a projection of the third via hole projected on the active layer is greater than 0 and less than or equal to 2 microns; removing regions of the gate insulating layer not covered by the source, the gate, and the drain; and conducting a second conductorization of the active layer. ### Claim 11 (depends on 10) The method for preparing a display panel as claimed in claim 10, wherein material of the active layer is indium gallium zinc oxide. ### Claim 12 (depends on 10) The method for preparing a display panel as claimed in claim 10, further comprising steps of: preparing a passivation layer on the buffer layer, wherein the passivation layer covers the second electrode plate, the source, the gate, and the drain; preparing a color resist layer on the passivation layer, wherein the color resist layer corresponds to a light transmitting region of the display panel; preparing a protective layer on the passivation layer, wherein the protective layer covers the color resist layer; etching the protective layer and the passivation layer to form a fourth via hole; preparing a pixel electrode layer on the protective layer, wherein the pixel electrode layer is connected to the source through the fourth via hole; and preparing a pixel definition layer on the protective layer and the pixel electrode layer. ### Claim 13 (depends on 12) The method for preparing a display panel as claimed in claim 12, further comprising steps of: preparing an organic light emitting layer on the pixel electrode layer; and preparing a common electrode layer the organic light emitting layer and the pixel definition layer. ### Claim 14 (depends on 12) The method for preparing a display panel as claimed in claim 12, wherein material of the pixel definition layer is hydrophobic material. ### Claim 15 (depends on 12) The method for preparing a display panel as claimed in claim 12, wherein material of the pixel definition layer is non-hydrophobic material. ### Claim 16 A display device comprising a driver chip and a display panel, wherein the display panel comprises: a substrate layer; a light shielding metal layer and a first electrode plate of a storage capacitor on the substrate layer; a buffer layer covering the light shielding metal layer and the first electrode plate on the substrate layer; an active layer and a second electrode plate of the storage capacitor on the buffer layer; a gate insulating layer on the buffer layer and the active layer, and a source, a gate and a drain on the gate insulating layer; wherein the source is connected to the light shielding metal layer through a first via hole; a second via hole and a third via hole are defined by the gate insulating layer, the source is connected to one side of the active layer through the second via hole, and the drain is connected to other side of the active layer through the third via hole; wherein widths of the source and the drain are both smaller than a width of the active layer, a range of a vertical distance between an edge of a projection of the source projected on the active layer and an edge of a projection of the second via hole projected on the active layer is greater than 0 and less than or equal to 2 microns, and a range of a vertical distance between an edge of a projection of the drain projected on the active layer and an edge of a projection of the third via hole projected on the active layer is greater than 0 and less than or equal to 2 microns. ### Claim 17 (depends on 16) The display device as claimed in claim 16, wherein material of the active layer is indium gallium zinc oxide. ### Claim 18 (depends on 16) The display device as claimed in claim 16, further comprising a passivation layer located on the buffer layer and covering the second electrode plate, the source, the gate, and the drain; a color resist layer located on the passivation layer and corresponding to a light transmitting region of the display panel; a protective layer located on the passivation layer and covering the color resist layer; a pixel electrode layer located on the protective layer; and a pixel definition layer located on the protective layer and the pixel electrode layer, wherein the pixel electrode layer is connected to the source through a fourth via hole. ### Claim 19 (depends on 18) The display device as claimed in claim 18, wherein material of the pixel definition layer is hydrophobic material. ### Claim 20 (depends on 18) The display device as claimed in claim 18, wherein material of the pixel definition layer is non-hydrophobic material.