# US 2022/0045149 A1 · Display apparatus and method of manufacturing the same

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- Number: US 2022/0045149 A1
- Document ID: US20220045149A1
- Status: Published application
- Kind: A1
- Application number: 17/291,008
- Filed: 2019-02-01
- Published: 2022-02-10
- Earliest claimed: 2018-11-08
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Cha-dong KIM; Youngdae KIM; Hyunae KIM; Chongsup CHANG; Eui-kang HEO
- Web page: https://patentgrep.com/patent/US20220045149A1

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)}
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 99/00: Subject matter not provided for in other groups of this subclass
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2320/029: by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
- G09G 2320/0693: Calibration of display systems
- G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A display apparatus includes a base substrate including a display region in which an image is displayed and a peripheral region that is a non-display region adjacent to the display region, a plurality of pixels disposed on the base substrate in the display region, each of the pixels including a thin film transistor that includes an oxide semiconductor pattern, a data driver disposed in the peripheral region and configured to provide a data voltage to the pixels, and a plurality of test patterns disposed on the base substrate in the peripheral region, each of the test patterns including a test thin film transistor that includes a test oxide semiconductor pattern.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A display apparatus comprising:
a base substrate including a display region in which an image is displayed and a peripheral region that is a non-display region disposed adjacent to the display region;
a plurality of pixels disposed on the base substrate in the display region, each of the pixels including a thin film transistor that includes a semiconductor pattern;
a plurality of drivers disposed in the peripheral region and configured to provide driving signals to the pixels; and
a plurality of test patterns disposed on the base substrate in the peripheral region between adjacent drivers, each of the test patterns including a test thin film transistor that includes a test semiconductor pattern.

### Claim 22 (depends on 21)

The display apparatus of claim 21, wherein the plurality of drivers are data drivers.

### Claim 23 (depends on 22)

The display apparatus of claim 22, wherein the test semiconductor pattern of the test pattern is formed to have a same material and a same shape as the semiconductor pattern of the pixel.

### Claim 24 (depends on 22)

The display apparatus of claim 22, further comprising:
a test lower conductive pattern disposed between the base substrate and the test semiconductor pattern; and
a lower conductive pattern disposed between the base substrate and the semiconductor pattern,
wherein the test thin film transistor further includes a test gate electrode that overlaps the test semiconductor pattern and a test source electrode and a test drain electrode that are electrically connected to the test semiconductor pattern, and
wherein the thin film transistor further includes a gate electrode that overlaps the semiconductor pattern and a source electrode and a drain electrode that are electrically connected to the semiconductor pattern.

### Claim 25 (depends on 24)

The display apparatus of claim 24, further comprising:
an interlayer insulating layer disposed between the test gate electrode and the test source electrode and the test drain electrode,
wherein each of the test patterns further includes:
a first test electrode disposed on the interlayer insulating layer and electrically connected to the test gate electrode via a contact hole that is formed through the interlayer insulating layer;
a second test electrode disposed on the interlayer insulating layer and electrically connected to the test source electrode; and
a third test electrode disposed on the interlayer insulating layer and electrically connected to the test drain electrode.

### Claim 26 (depends on 25)

The display apparatus of claim 25, further comprising:
an intermetal dielectric layer disposed on the thin film transistor;
a first electrode disposed on the intermetal dielectric layer and electrically connected to the drain electrode of the thin film transistor;
a light emitting layer disposed on the first electrode; and
a second electrode disposed on the light emitting layer.

### Claim 27 (depends on 26)

The display apparatus of claim 26, further comprising:
an opposite substrate disposed on the base substrate and disposed to be spaced apart from the test pattern in a plan view.

### Claim 28 (depends on 22)

The display apparatus of claim 22, wherein the data driver is an integrated circuit chip mounted on the base substrate.

### Claim 29 (depends on 22)

The display apparatus of claim 22, further comprising:
right-first and right-second power lines disposed on a right side of the test pattern with respect to the test pattern disposed between the two adjacent data drivers; and
left-first and left-second power lines disposed on a left side of the test pattern with respect to the test pattern disposed between the two adjacent data drivers,
wherein the right-first power line and the right-second power line extend from the data driver that is disposed on the right side of the test pattern and provide first power and second power to corresponding pixels in the display region, and
wherein the left-first power line and the left-second power line extend from the data driver that is disposed on the left side of the test pattern and provide the first power and the second power to corresponding pixels in the display region.

### Claim 30 (depends on 22)

The display apparatus of claim 22, wherein the test patterns are disposed to be spaced apart from each other along a length direction of the peripheral region.

### Claim 31 (depends on 22)

The display apparatus of claim 22, further comprising:
a test region disposed adjacent to the peripheral region,
wherein the peripheral region is disposed between the test region and the display region, and
wherein a plurality of test pads that are electrically connected to the pixels of the display region are formed in the test region.

### Claim 32 (depends on 22)

The display apparatus of claim 22, wherein the test region is cut and removed after a test of the display apparatus is completed.

### Claim 33 (depends on 32)

The display apparatus of claim 32, further comprising:
a compensation circuit part electrically connected to the test patterns and configured to sense a characteristic of the test thin film transistor of each of the test patterns and to compensate for a driving voltage based on an average and a distribution of the characteristic.

### Claim 34 (depends on 33)

The display apparatus of claim 33, wherein the characteristic is a threshold voltage of the test thin film transistor and the driving voltage is the data voltage.

### Claim 35 (depends on 34)

The display apparatus of claim 34, wherein the compensation circuit part includes:
a driving part configured to provide a test driving voltage to the test thin film transistor of the each of the test patterns;
a sensing part configured to receive a test signal from the test thin film transistor and to sense the characteristic of the test thin film transistor; and
a compensating part configured to compensate for the driving voltage using the characteristic that is sensed.

### Claim 36 (depends on 35)

The display apparatus of claim 35, wherein the compensation circuit part further includes:
a storing part configured to store the characteristic that the sensing part senses; and
a voltage generating part configured to provide the compensated driving voltage to the data driver.

### Claim 37

A display apparatus which includes a display region in which a plurality of pixels are disposed and a peripheral region that is a non-display region disposed adjacent to the display region, the display apparatus comprising:
a thin film transistor disposed in the display region and including a semiconductor; and
a plurality of test patterns disposed in the peripheral region between adjacent drivers,
wherein each of the test patterns includes a test thin film transistor including the semiconductor.

### Claim 38 (depends on 37)

The display apparatus of claim 37, wherein the drivers are data drivers.

### Claim 39 (depends on 38)

The display apparatus of claim 38, wherein a channel of the test thin film transistor is formed to have a same material and a same shape as a channel of the thin film transistor in the display region.

### Claim 40 (depends on 39)

The display apparatus of claim 39, further comprising:
a compensation circuit part electrically connected to the test patterns and configured to sense a characteristic of the test thin film transistor of each of the test patterns and to compensate for a driving voltage based on an average and a distribution of the characteristic.