# US 2022/0045129 A1 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045129 A1 - Document ID: US20220045129A1 - Status: Published application - Kind: A1 - Application number: 17/187,626 - Filed: 2021-02-26 - Published: 2022-02-10 - Earliest claimed: 2020-08-06 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Hiroyuki HARA; Yoshinori SUZUKI - Web page: https://patentgrep.com/patent/US20220045129A1 ## CPC - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/8413: {adapted for resistive heating} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - G11C 2213/71: Three dimensional array - G11C 2213/72: Array wherein the access device being a diode - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines. ## Claims ### Claim 1 A semiconductor storage device comprising: a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines; a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent; a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line; a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells, wherein a memory cell from each of the logical slices is selected when carrying out a read operation or a write operation on the memory cell array, and the logical slices of memory cells include first and second logical slices, the first logical slice including a first memory cell electrically connected between the first outer lower bit line and the first word line, a second memory cell electrically connected between the first outer lower bit line and the second word line, a third memory cell electrically connected between the first inner upper bit line and the second word line, and a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and the second logical slice including a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line, a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line, a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and an eighth memory cell electrically connected between the first outer upper bit line and the first word line. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein a selected bit line voltage is applied to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice to which data is to be written, and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice to which data is to be written; and a selected word line voltage is applied to the first word line when the eighth memory cell is selected as the memory cell of the second logical slice to which data is to be written, and to the fifth word line when the seventh memory cell is selected as the memory cell of the second logical slice to which data is to be written. ### Claim 3 (depends on 2) The semiconductor storage device according to claim 2, further comprising: a first write register in which the data to be written to the selected memory cell is stored when the selected memory cell is the eighth memory cell; a first write circuit configured to write the data stored in the first write register to the eighth memory cell; a second write register in which the data to be written to the selected memory cell is stored when the selected memory cell is the seventh memory cell; and a second write circuit configured to write the data stored in the second write register to the seventh memory cell. ### Claim 4 (depends on 2) The semiconductor storage device according to claim 2, further comprising: a write register in which the data to be written to the selected memory cell of the second logical slice is stored; a first write circuit configured to write the data stored in the write register to the eighth memory cell; and a second write circuit configured to write the data stored in the write register to the seventh memory cell. ### Claim 5 (depends on 1) The semiconductor storage device according to claim 1, wherein a selected bit line voltage is applied to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read, and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read; and a selected word line voltage is applied to the first word line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read, and to the fifth word line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read. ### Claim 6 (depends on 5) The semiconductor storage device according to claim 5, further comprising: a first read circuit configured to read the data from the eighth memory cell when the selected memory cell is the eighth memory cell; a first read register in which the data read from the eighth memory cell is stored by the first read circuit; a second read circuit configured to read the data from the seventh memory cell when the selected memory cell is the seventh memory cell; and a second read register in which the data read from the seventh memory cell is stored by the second read circuit. ### Claim 7 (depends on 5) The semiconductor storage device according to claim 5, further comprising: a read register in which the data read from the selected memory cell of the second logical slice is stored; a first read circuit configured to read the data from the eighth memory cell and store the data in the read register when the selected memory cell is the eighth memory cell; and a second read circuit configured to read the data from the seventh memory cell and store the data in the read register when the selected memory cell is the seventh memory cell. ### Claim 8 (depends on 1) The semiconductor storage device according to claim 1, wherein the plurality of lower bit lines are spaced apart in the first direction; and the plurality of upper bit lines are spaced apart in the first direction. ### Claim 9 (depends on 1) The semiconductor storage device according to claim 1, wherein the number of word lines electrically connected to each of the lower bit lines and the inner upper bit lines is the same, and the number of word lines electrically connected to each of the first and second outer upper bit lines is one-half of the number of word lines electrically connected to each of the lower bit lines and the inner upper bit lines. ### Claim 10 (depends on 1) The semiconductor storage device according to claim 1, further comprising: a first multiplexer circuit configured to supply a selected bit line voltage to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read or to which data is to be written; and a second multiplexer circuit configured to supply the selected bit line voltage to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read or to which data is to be written to the second outer bit line. ### Claim 11 (depends on 10) The semiconductor storage device according to claim 10, further comprising: a third multiplexer circuit configured to supply a selected word line voltage to the first word line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read or to which data is to be written; and a fourth multiplexer circuit configured to supply the selected word line voltage to the fifth word line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read or to which data is to be written to the second outer bit line. ### Claim 12 A method of performing a write operation in a semiconductor storage device comprising: a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines; a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent; a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line; and a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells, said method comprising selecting a memory cell from each of the logical slices, wherein the logical slices of memory cells include first and second logical slices, the first logical slice including a first memory cell electrically connected between the first outer lower bit line and the first word line, a second memory cell electrically connected between the first outer lower bit line and the second word line, a third memory cell electrically connected between the first inner upper bit line and the second word line, and a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and the second logical slice including a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line, a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line, a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and an eighth memory cell electrically connected between the first outer upper bit line and the first word line, and applying a selected bit line voltage to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice to which data is to be written and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice to which data is to be written. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: applying a selected word line voltage to the first word line when the eighth memory cell is selected as the memory cell of the second logical slice to which data is to be written and to the fifth word line when the seventh memory cell is selected as the memory cell of the second logical slice to which data is to be written. ### Claim 14 (depends on 13) The method according to claim 13, further comprising: storing the data to be written in a first write register when the selected memory cell is the eighth memory cell and in a second write register when the selected memory cell is the seventh memory cell. ### Claim 15 (depends on 13) The method according to claim 13, further comprising: storing the data to be written in a write register when the selected memory cell is either the seventh memory cell or the eighth memory cell. ### Claim 16 A method of performing a read operation in a semiconductor storage device comprising: a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines; a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent; a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line; and a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells, said method comprising selecting a memory cell from each of the logical slices, wherein the logical slices of memory cells include first and second logical slices, the first logical slice including a first memory cell electrically connected between the first outer lower bit line and the first word line, a second memory cell electrically connected between the first outer lower bit line and the second word line, a third memory cell electrically connected between the first inner upper bit line and the second word line, and a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and the second logical slice including a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line, a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line, a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and an eighth memory cell electrically connected between the first outer upper bit line and the first word line, and applying a selected bit line voltage to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: applying a selected word line voltage to the first word line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read and to the fifth word line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read. ### Claim 18 (depends on 17) The method according to claim 17, further comprising: storing the data read from the selected memory cell in a first read register when the selected memory cell is the eighth memory cell and in a second read register when the selected memory cell is the seventh memory cell. ### Claim 19 (depends on 17) The method according to claim 17, further comprising: storing the data read from the selected memory cell in a read register when the selected memory cell is either the seventh memory cell or the eighth memory cell.