# US 2022/0045100 A1 · Channel hole and bitline architecture and method to improve page or block size and performance of 3d nand

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- Number: US 2022/0045100 A1
- Document ID: US20220045100A1
- Status: Published application
- Kind: A1
- Application number: 17/509,195
- Filed: 2021-10-25
- Published: 2022-02-10
- Earliest claimed: 2019-02-18
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Jun LIU
- Web page: https://patentgrep.com/patent/US20220045100A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/42: Vias, e.g. via plugs
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The method includes forming an alternating layer stack, forming a plurality of slit structures, forming a plurality of conductor/dielectric layer pairs, forming a first column of vertical memory strings, forming a second column of vertical memory strings, and forming a plurality of bitlines. The plurality of slit structures each extend vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger. The vertical memory strings in the first column are displaced relative to each other along the wordline direction. The vertical memory strings in the second column are displaced relative to each other along the wordline direction. Each bitline is connected to an individual vertical memory string in the first and second columns.

## Claims

### Claim 1

A method for forming a memory finger in a three-dimensional memory device, comprising:
forming, on a substrate, an alternating layer stack;
forming a plurality of slit structures each extending vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger;
forming, in the alternating layer stack, a plurality of conductor/dielectric layer pairs;
forming a first column of vertical memory strings extending through the alternating layer stack in the at least one memory finger, wherein the vertical memory strings in the first column are displaced relative to each other along the wordline direction;
forming a second column of vertical memory strings extending through the alternating layer stack in the at least one memory finger, wherein the vertical memory strings in the second column are displaced relative to each other along the wordline direction; and
forming a plurality of bitlines displaced along the wordline direction and extending along a bitline direction in the at least one memory finger, wherein each bitline is connected to an individual vertical memory string in the first and second columns.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the plurality of bitlines comprises quadruple patterning the plurality of bitlines.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
forming the vertical memory strings of the first column comprises evenly displacing the vertical memory strings of the first column relative to each other along the wordline direction; and
forming the vertical memory strings of the second column comprises evenly displacing the vertical memory strings of the second column relative to each other along the wordline direction.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the vertical memory strings of the first column are displaced relative to each other by a relative distance of about 1 nm to about 10 nm; and
the vertical memory strings of the second column are displaced relative to each other by a relative distance of about 1 nm to about 10 nm.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a continuous top select gate along the bitline direction and connected to the first and second columns of vertical memory strings in the at least one memory finger.

### Claim 6 (depends on 1)

The method of claim 1, wherein:
forming the first column of vertical memory strings comprises forming the first column of vertical memory strings along a first angle relative to the bitline direction; and
forming the second column of vertical memory strings comprises forming the second column of vertical memory strings along a second angle relative to the bitline direction.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the first and second columns of vertical memory strings comprises arranging the first and second angles to be equal.

### Claim 8 (depends on 6)

The method of claim 6, wherein forming the first and second columns of vertical memory strings comprises arranging the first and second angles to be different.

### Claim 9 (depends on 6)

The method of claim 6, wherein:
forming the first column of vertical memory strings comprises forming at least four vertical memory strings within the at least one memory finger and along the first angle; and
forming the second column of vertical memory strings comprises forming at least four vertical memory strings within the at least one memory finger and along the second angle.

### Claim 10 (depends on 6)

The method of claim 6, wherein forming the second column of vertical memory strings comprises offsetting the second column of vertical memory strings along the bitline direction relative to the first column of vertical memory strings, such that each vertical memory string of the second column of vertical memory strings is disposed between adjacent vertical memory strings of the first column of vertical memory strings along the bitline direction.

### Claim 11

A method for forming a memory finger in a three-dimensional memory device, comprising:
forming a first column of memory cells extending through an alternating layer stack, wherein the memory cells of the first column are displaced relative to each other along a wordline direction;
forming a second column of memory cells extending through the alternating layer stack, wherein the memory cells in the second column are displaced relative to each other along the wordline direction; and
forming a plurality of bitlines displaced along the wordline direction and extending along a bitline direction, wherein each bitline is connected to an individual memory cell in the first and second columns,
wherein the first and second columns of memory cells are formed within a memory finger.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the second column of memory cells comprises offsetting the second column of memory cells along the bitline direction relative to the first column of memory cells, such that each memory cell of the second column of memory cells is disposed between adjacent memory cells of the first column of memory cells along the bitline direction.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
forming the first and second columns of memory cells comprises defining a channel hole pitch along the wordline direction.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the first and second columns of memory cells comprises arranging the channel hole pitch between the first and second columns of memory cells along the wordline direction to be less than 1.

### Claim 15 (depends on 11)

The method of claim 11, wherein:
forming first and second columns of memory cells comprises defining a channel hole pitch along the wordline direction; and
forming the plurality of bitlines comprises defining a bitline pitch along the bitline direction.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first and second columns of memory cells and the plurality of bitlines comprises arranging the channel hole pitch to be greater than ten times the bitline pitch.

### Claim 17 (depends on 11)

The method of claim 11, wherein:
forming the first column of memory cells comprises forming the first column of memory cells along a first angle relative to the bitline direction; and
forming the second column of memory cells comprises forming the second column of memory cells along a second angle relative to the bitline direction.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
forming the first column of memory cells comprises forming at least four memory cells within the memory finger and along the first angle; and
forming the second column of memory cells comprises forming at least four memory cells within the memory finger and along the second angle.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
forming the first column of memory cells comprises forming at least five memory cells within the memory finger and along the first angle; and
forming the second column of memory cells comprises forming at least five memory cells within the memory finger and along the second angle.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
forming the first column of memory cells comprises forming six memory cells within the memory finger and along the first angle; and
forming the second column of memory cells comprises forming six memory cells within the memory finger and along the second angle.