# US 2022/0045099 A1 · Three-dimensional flash memory device with increased storage density > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045099 A1 - Document ID: US20220045099A1 - Status: Published application - Kind: A1 - Application number: 17/500,370 - Filed: 2021-10-13 - Published: 2022-02-10 - Earliest claimed: 2019-06-28 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Min She; Qiang Tang - Web page: https://patentgrep.com/patent/US20220045099A1 ## CPC - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10W 20/43: Layouts of interconnections - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A 3D flash memory device includes a substrate having a substantial planar surface. A plurality of active columns of semiconducting material is disposed above the substrate. Each of the plurality of active columns extends along a first direction orthogonal to the planar surface of the substrate. The plurality of active columns is arranged in a two-dimensional array. Each of the plurality of active columns may comprise multiple local bit lines and multiple local source lines extending along the first direction. Multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. A word line stack wraps around the plurality of active columns. A charge-storage element is disposed between the word line stack and each of the plurality of active columns. ## Claims ### Claim 1 (canceled) ### Claim 2 A three-dimensional flash memory device, comprising: a substrate; a column of semiconducting material disposed above the substrate, extending along a vertical direction; a word line stack wrapping around the column; and a charge-storage element disposed between the word line stack and the column, wherein the column, the charge-storage element, and the word line stack constitutes at least two memory cells. ### Claim 3 (depends on 2) The three-dimensional flash memory device according to claim 2, wherein two of the at least two memory cells comprise a common local source line extending along the vertical direction. ### Claim 4 (depends on 3) The three-dimensional flash memory device according to claim 3, wherein two of the at least two memory cells comprise a channel breaker extending along the vertical direction and separating the two of the at least two memory cells. ### Claim 5 (depends on 4) The three-dimensional flash memory device according to claim 4, wherein the channel breaker comprises an insulating layer. ### Claim 6 (depends on 4) The three-dimensional flash memory device according to claim 4, wherein the column comprises at least two local bit lines and the common local source line extending along the vertical direction, and the channel breaker separating the at least two memory cells by separating the at least two local bit lines. ### Claim 7 (depends on 6) The three-dimensional flash memory device according to claim 6, wherein the word line stack comprising a word line extends along a second direction that is perpendicular to the vertical direction. ### Claim 8 (depends on 7) The three-dimensional flash memory device according to claim 7, wherein the two of the at least two memory cells are configured to be controlled by the word line and the at least two local bit lines. ### Claim 9 (depends on 7) The three-dimensional flash memory device according to claim 7, wherein the at least two local bit lines are electrically coupled to two global bit lines, respectively. ### Claim 10 (depends on 9) The three-dimensional flash memory device according to claim 9, wherein the two global bit lines extend along a third direction that is perpendicular to the second direction and the vertical direction. ### Claim 11 (depends on 9) The three-dimensional flash memory device according to claim 9, wherein the two global bit lines is electrically coupled to a select transistor, wherein the select transistor connects the two global bit lines to the at least two local bit lines. ### Claim 12 A three-dimensional flash memory device, comprising: a substrate; multiple columns of semiconducting material disposed above the substrate, each of the multiple columns extending along a vertical direction; a word line stack wrapping around the multiple columns; and a charge-storage element disposed between the word line stack and each of the multiple columns, wherein each of the multiple columns, the charge-storage element, and the word line stack constitute multiple memory cells. ### Claim 13 (depends on 12) The three-dimensional flash memory device according to claim 12, wherein the multiple memory cells comprise at least one common local source line extending along the vertical direction. ### Claim 14 (depends on 13) The three-dimensional flash memory device according to claim 13, wherein each of the multiple columns comprises multiple local bit lines and multiple local source lines extending along the vertical direction, and multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. ### Claim 15 (depends on 14) The three-dimensional flash memory device according to claim 14, wherein each two of the multiple memory cells comprise at least two local bit lines and the at least one common local source line extending along the vertical direction. ### Claim 16 (depends on 15) The three-dimensional flash memory device according to claim 15, wherein the word line stack comprising a word line extends along a second direction that is perpendicular to the vertical direction. ### Claim 17 (depends on 16) The three-dimensional flash memory device according to claim 16, wherein each two of the multiple memory cells are configured to be controlled by a word line and the at least two local bit lines. ### Claim 18 (depends on 16) The three-dimensional flash memory device according to claim 16, wherein the multiple local bit lines are electrically coupled to multiple global bit lines, respectively. ### Claim 19 (depends on 18) The three-dimensional flash memory device according to claim 18, wherein the multiple global bit lines extend along a third direction that is perpendicular to the second direction and the vertical direction. ### Claim 20 (depends on 18) The three-dimensional flash memory device according to claim 18, wherein each of the multiple global bit lines is electrically coupled to a select transistor, wherein the select transistor connects the multiple global bit lines to the multiple local bit lines. ### Claim 21 (depends on 14) The three-dimensional flash memory device according to claim 14, further comprising: a channel breaker between two of the multiple local bit lines.