# US 2022/0045096 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045096 A1 - Document ID: US20220045096A1 - Status: Published application - Kind: A1 - Application number: 17/198,592 - Filed: 2021-03-11 - Published: 2022-02-10 - Earliest claimed: 2020-08-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyo Joon RYU; Seo-Goo KANG; Hee Suk KIM; Jong Seon AHN; Kohji KANAMORI; Jee Hoon HAN - Web page: https://patentgrep.com/patent/US20220045096A1 ## CPC - H10B 41/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/10: characterised by the top-view layout - H10W 20/42: Vias, e.g. via plugs - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line. ## Claims ### Claim 1 A semiconductor memory device, comprising: a lower stacked structure extending in a first direction on a substrate, the lower stacked structure including a plurality of lower metal lines stacked in a vertical direction; an upper stacked structure on the lower stacked structure, the upper stacked structure including at least one upper metal line; at least one vertical structure penetrating the upper stacked structure and the lower stacked structure in the vertical direction, the at least one vertical structure including a channel layer; a first cutting line through the upper stacked structure and the lower stacked structure; a recess on the first cutting line; an upper supporter on the first cutting line, the upper supporter being inside the recess; a second cutting line through the upper stacked structure and the lower stacked structure, the second cutting line being spaced apart from the first cutting line in the first direction; at least one sub-cutting line through the upper stacked structure while at least partially overlapping the at least one vertical structure in the vertical direction, the at least one sub-cutting line being between the first cutting line and the second cutting line, and a top surface of the upper supporter being coplanar with a top surface of the at least one sub-cutting line; and a first interlayer insulating layer surrounding a sidewall of the upper supporter and a sidewall of the at least one sub-cutting line. ### Claim 2 (depends on 1) The semiconductor memory device as claimed in claim 1, further comprising a second interlayer insulating layer between an uppermost surface of the at least one vertical structure and the first interlayer insulating layer, wherein the second interlayer insulating layer surrounds a sidewall of the first cutting line, a sidewall of the second cutting line, and the sidewall of the at least one sub-cutting line, and wherein at least a part of a bottom surface of the upper supporter is in contact with a top surface of the second interlayer insulating layer. ### Claim 3 (depends on 1) The semiconductor memory device as claimed in claim 1, further comprising: a third interlayer insulating layer on the top surface of the upper supporter and the first interlayer insulating layer; and a bit line extending in the first direction on the third interlayer insulating layer and spaced apart from the upper supporter in the vertical direction. ### Claim 4 (depends on 3) The semiconductor memory device as claimed in claim 3, wherein the at least one vertical structure includes: a first vertical structure connected to the bit line; and a second vertical structure overlapping the at least one sub-cutting line in the vertical direction without being connected to the bit line. ### Claim 5 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein: the at least one vertical structure includes a plurality of vertical structures, and the at least one sub-cutting line includes: a first sub-cutting line spaced apart from the first cutting line in the first direction, and a second sub-cutting line spaced apart from the first sub-cutting line in the first direction, at least two of the plurality of vertical structures being spaced apart from each other in the first direction between the first sub-cutting line and the second sub-cutting line. ### Claim 6 (depends on 5) The semiconductor memory device as claimed in claim 5, wherein the at least one sub-cutting line further includes a third sub-cutting line spaced apart from the second sub-cutting line in the first direction, at least two additional ones of the plurality of vertical structures being spaced apart from each other in the first direction between the second sub-cutting line and the third sub-cutting line. ### Claim 7 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein a bottom surface of the at least one sub-cutting line is between the lower stacked structure and the upper stacked structure. ### Claim 8 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein a height of the at least one sub-cutting line in the vertical direction ranges from 5000 angstroms to 10000 angstroms. ### Claim 9 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the at least one sub-cutting line overlaps the channel layer in the vertical direction. ### Claim 10 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein a first width of a top surface of the first cutting line in the first direction is smaller than a second width of a bottom surface of the upper supporter in the first direction. ### Claim 11 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein a third width of the top surface of the at least one sub-cutting line in the first direction is greater than a fourth width of an uppermost surface of the at least one vertical structure in the first direction. ### Claim 12 (depends on 1) The semiconductor memory device as claimed in claim 1, wherein the at least one upper metal line includes a first upper metal line and a second upper metal line on the first upper metal line. ### Claim 13 (depends on 12) The semiconductor memory device as claimed in claim 12, wherein: the first upper metal line includes a first sub-upper metal line and a second sub-upper metal line on the first sub-upper metal line, and the second upper metal line includes a third sub-upper metal line and a fourth sub-upper metal line on the third sub-upper metal line. ### Claim 14 A semiconductor memory device, comprising: a lower stacked structure extending in a first direction on a substrate, the lower stacked structure including lower metal lines stacked in a vertical direction; an upper stacked structure on the lower stacked structure, the upper stacked structure including at least one upper metal line; at least one vertical structure penetrating the upper and lower stacked structures in the vertical direction, the at least one vertical structure including a channel layer; a first cutting line through the upper and lower stacked structures; a first upper supporter on the first cutting line; a second upper supporter on the first cutting line, the second upper supporter being spaced apart from the first upper supporter in a second direction different from the first direction; and at least one sub-cutting line through the upper stacked structure while at least partially overlapping the at least one vertical structure in the vertical direction, the at least one sub-cutting line being spaced apart from the first cutting line in the first direction, and a top surface of the first upper supporter being coplanar with a top surface of the at least one sub-cutting line. ### Claim 15 (depends on 14) The semiconductor memory device as claimed in claim 14, further comprising: an interlayer insulating layer on the top surface of the first upper supporter; and a bit line extending in the first direction on the interlayer insulating layer, the bit line being spaced apart from the first upper supporter in the vertical direction, wherein the at least one vertical structure includes: a first vertical structure connected to the bit line, and a second vertical structure overlapping the at least one sub-cutting line in the vertical direction without being connected to the bit line. ### Claim 16 (depends on 14) The semiconductor memory device as claimed in claim 14, wherein: the at least one vertical structure includes a plurality of vertical structures, and the at least one sub-cutting line includes: a first sub-cutting line spaced apart from the first cutting line in the first direction, and a second sub-cutting line spaced apart from the first sub-cutting line in the first direction, at least two of the plurality of vertical structures being spaced apart from each other in the first direction between the first sub-cutting line and the second sub-cutting line. ### Claim 17 (depends on 14) The semiconductor memory device as claimed in claim 14, wherein a bottom surface of the at least one sub-cutting line is between the lower stacked structure and the upper stacked structure. ### Claim 18 (depends on 14) The semiconductor memory device as claimed in claim 14, wherein a first width of a top surface of the first cutting line in the first direction is smaller than a second width of a bottom surface of the first upper supporter in the first direction. ### Claim 19 (depends on 14) The semiconductor memory device as claimed in claim 14, wherein a first thickness of the at least one upper metal line in the vertical direction is greater than a second thickness of the lower metal line in the vertical direction. ### Claim 20 A semiconductor memory device, comprising: a base substrate; a horizontal conductive substrate on the base substrate; a lower stacked structure extending in a first direction on the horizontal conductive substrate, the lower stacked structure including a plurality of lower metal lines stacked in a vertical direction; an upper stacked structure on the lower stacked structure, the upper stacked structure including at least one upper metal line; a vertical structure penetrating the upper and lower stacked structures in the vertical direction, the vertical structure including a channel layer, and being electrically connected to the horizontal conductive substrate; a first cutting line through the upper and lower stacked structures, the first cutting line having a first width in the first direction; a first upper supporter on the first cutting line, the first upper supporter having a second width in the first direction greater than the first width; a second upper supporter on the first cutting line, the second upper supporter having the second width in the first direction, and being spaced apart from the first upper supporter in a second direction different from the first direction; a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line in the first direction; a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first cutting line and the second cutting line; a first interlayer insulating layer on the vertical structure and surrounding a sidewall of the first cutting line, a sidewall of the second cutting line, and a sidewall of the sub-cutting line; a second interlayer insulating layer on the first interlayer insulating layer and surrounding a sidewall of the first upper supporter and the sidewall of the sub-cutting line; and a bit line extending in the first direction on the second interlayer insulating layer, wherein a top surface of the first upper supporter is coplanar with a top surface of the sub-cutting line, and wherein at least a part of a bottom surface of the first upper supporter is in contact with a top surface of the first interlayer insulating layer.