# US 2022/0045093 A1 · Semiconductor device and a manufacturing method of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045093 A1 - Document ID: US20220045093A1 - Status: Published application - Kind: A1 - Application number: 17/165,593 - Filed: 2021-02-02 - Published: 2022-02-10 - Earliest claimed: 2020-08-07 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Nam Jae LEE - Web page: https://patentgrep.com/patent/US20220045093A1 ## CPC - H10B 41/40: characterised by the peripheral circuit region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 72/90: Bond pads, in general - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/941: {Dispositions of bond pads} - H10W 80/732: {having shape changed during the connecting} - H10W 90/792: {between multiple chips} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes: a substrate; a first connection structure disposed on the substrate, the first connection structure Including a first connection conductor; a transistor disposed between the substrate and the first connection structure; a first bonding structure Including a first bonding pad connected to the first connection conductor; a second bonding structure including a second bonding pad connected to the first bonding pad; a second connection structure including a second connection conductor connected to the second bonding pad; a stack structure disposed on the second connection structure; a channel structure penetrating the stack structure; and a chip guard penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip guard surrounding the stack structure and the channel structure. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a first connection structure disposed on the substrate, the first connection structure including a first connection conductor; a transistor disposed between the substrate and the first connection structure, the transistor being connected to the first connection conductor; a first bonding structure including a first bonding pad connected to the first connection conductor, the first bonding structure being disposed on the first connection structure; a second bonding structure including a second bonding pad connected to the first bonding pad, the second bonding structure being disposed on the first bonding structure; a second connection structure including a second connection conductor connected to the second bonding pad, the second connection structure being disposed on the second bonding structure; a stack structure disposed on the second connection structure, the stack structure including alternately stacked insulating layers and conductive patterns; a channel structure penetrating the stack structure, the channel structure being connected to the second connection conductor; and a chip guard penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure, the chip guard surrounding the stack structure and the channel structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first bonding pad and the second boding pad include copper. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the chip guard includes: first guard parts in the first connection structure; and a second guard part penetrating the second connection structure, the second bonding structure, and the first bonding structure. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the first guard parts overlap with each other. ### Claim 5 (depends on 3) The semiconductor device of claim 3, wherein the second guard part includes: a conductive part penetrating the second connection structure, the second bonding structure, and the first bonding structure; and a barrier part surrounding the conductive part. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the conductive part and the barrier part include different materials. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the barrier part includes titanium or tantalum. ### Claim 8 (depends on 5) The semiconductor device of claim 5, wherein the barrier part covers a sidewall and a bottom surface of the conductive part. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising a source structure including a source layer connected to the channel structure, the source structure being disposed on the stack structure. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the chip guard penetrates the source structure. ### Claim 11 (depends on 3) The semiconductor device of claim 3, wherein the second guard part fills a through slit penetrating the second connection structure, the second bonding structure, the first bonding structure, and the first connection structure. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the second guard part includes: a barrier part covering a sidewall and a bottom surface of the through slit; and a conductive part in the barrier part. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a side all of the barrier part extends from the second connection structure to the first connection structure. ### Claim 14 A semiconductor device comprising: a transistor; a first connection conductor connected to the transistor; a first bonding pad connected to the first connection conductor; a second bonding pad connected to the first bonding pad; a second connection conductor connected to the second bonding pad; a channel structure connected to the second connection conductor; and a chip guard including a first guard part and a second guard part on the first guard part, wherein the second guard part surrounds the first bonding pad, the second bonding pad, the second connection conductor, and the channel structure. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the second guard part penetrates a bonding interface between the first bonding pad and the second bonding pad. ### Claim 16 (depends on 14) The semiconductor device of claim 14, wherein the second guard part includes: a conductive part; and a barrier part covering a sidewali and a bottom surface of the conductive part. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the conductive part and the barrier part penetrate the bonding interface between the first bonding pad and the second bonding pad. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein: the conductive part is spaced apart from the first guard part; and the barrier part is in contact with the first guard part. ### Claim 19 A semiconductor device comprising: a transistor; a first connection conductor connected to the transistor; a first bonding pad connected to the first connection conductor; a second bonding pad connected to the first bonding pad; a second connection conductor connected to the second bonding pad; a channel structure connected to the second connection conductor; a stack structure surrounding the channel structure; and a chip guard surrounding the first connection conductor, the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stack structure, wherein the chip guard includes a first guard part and a second guard part on the first guard part, and wherein the first bonding pad, the second bonding pad, the second connection conductor, the channel structure, and the stack structure are disposed at a level higher than a level of a bottom surface of the second guard part and lower than a level of a top surface of the second guard part. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the second guard part includes first parts extending in a first direction, the first parts being spaced apart from each other in a second direction intersecting the first direction, wherein the stack structure is disposed between the first parts, and wherein a length of each of the first parts in the first direction is greater than a length of the stack structure in the first direction.