# US 2022/0045092 A1 · Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0045092 A1
- Document ID: US20220045092A1
- Status: Published application
- Kind: A1
- Application number: 16/985,410
- Filed: 2020-08-05
- Published: 2022-02-10
- Earliest claimed: 2020-08-05
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Zhixin CUI; Satoshi SHIMIZU; Yanli ZHANG
- Web page: https://patentgrep.com/patent/US20220045092A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- G11C 8/14: Word line organisation; Word line lay-out
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/42: Vias, e.g. via plugs
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise source-select-level electrically conductive layers and word-line-level electrically conductive layers overlying the source-select-level electrically conductive layers;
a source contact layer located between the substrate and the alternating stack;
a memory opening vertically extending through the alternating stack and the source contact layer with a width-modulated vertical cross-sectional profile that has a first width at and below levels of the source-select-level electrically conductive layers, and has a second width that is greater than the first width at levels of a first subset of the word-line-level electrically conductive layers; and
a memory opening fill structure located within the memory opening and comprising a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel, wherein the composite semiconductor channel comprises:
a pedestal channel portion located within a portion of the memory opening having the first width and having a cylindrical sidewall segment that contacts the source contact layer; and
a vertical semiconductor channel contacting a top surface of the pedestal channel portion and extending through the word-line-level electrically conductive layers.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein the memory opening comprises an annular bottom surface that connects a top periphery of a first cylindrical sidewall of the memory opening extending through the source-select-level electrically conductive layers and a bottom periphery of a second cylindrical sidewall of the memory opening extending through the first subset of the word-line-level electrically conductive layers.

### Claim 3 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the memory opening has a third width that is less than the second width at levels of a second subset of the word-line-level electrically conductive layers that overlie the first subset of the word-line-level electrically conductive layers; and
the vertical semiconductor channel vertically extends through each layer within the second subset of the word-line-level electrically conductive layers.

### Claim 4 (depends on 3)

The three-dimensional memory device of claim 3, wherein:
the top surface of the pedestal channel portion is located between a horizontal plane including a bottom surface of a bottommost one of the word-line-level electrically conductive layers and a horizontal plane including a top surface of a topmost one of the source-select-level electrically conductive layers; and
a void that is free of any solid phase material is located within a portion of the memory opening having the second width, and is laterally surrounded by a dielectric core located inside the vertical semiconductor channel.

### Claim 5 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the memory film comprises a concave annular bottom surface segment that contacts the source contact layer; and
an outer periphery of the concave annular bottom surface is located at a greater vertical distance from the substrate than an inner periphery of the concave annular bottom surface is from the substrate.

### Claim 6 (depends on 1)

The three-dimensional memory device of claim 1, wherein the pedestal channel portion contacts the source contact layer at a cylindrical interface located within a cylindrical vertical plane located at or inside an inner sidewall of a portion of the memory film that extends through the source-select-level electrically conductive layers.

### Claim 7 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the memory opening fill structure comprises a bottom dielectric cap structure having a same set of material compositions as component layers of the memory film, and contacting a bottom surface of the pedestal channel portion; and
the bottom dielectric cap structure comprises a concave annular surface that contacts the source contact layer.

### Claim 8 (depends on 7)

The three-dimensional memory device of claim 7, wherein:
a bottom periphery of an outer sidewall of a portion of the memory film extending through the source-select-level electrically conductive layers and a top periphery of an outer sidewall of the bottom dielectric cap structure have a same horizontal cross-sectional shape and overlap with each other in a plan view; and
each of the memory film and the bottom dielectric cap structure comprises a layer stack including, from one side to another, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.

### Claim 9 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the pedestal channel portion includes at least one of carbon and arsenic as dopant atoms at a first average dopant concentration; and
the vertical semiconductor channel includes the at least one of carbon or arsenic dopant atoms at a second average dopant concentration that is less than 20% of the first average dopant concentration or is free of the at least one of carbon or arsenic dopants atoms.

### Claim 10 (depends on 9)

The three-dimensional memory device of claim 9, wherein:
the pedestal channel portion comprises polysilicon containing carbon atoms at an average atomic concentration in a range from 5.0×1017 atoms/cm3 to 2.0×1021 atoms/cm3; and
the vertical semiconductor channel comprises polysilicon containing carbon atoms at an average atomic concentration less than 1.0×1017 atoms/cm3 or is free of carbon atoms.

### Claim 11 (depends on 10)

The three-dimensional memory device of claim 10, wherein:
the pedestal channel portion comprises n-type dopant atoms at an average atomic concentration in a range from 1.0×1018 atoms/cm3 to 1.0×1020 atoms/cm3; and
the vertical semiconductor channel includes n-type dopant atoms at an average atomic concentration of than 1.0×1017 atoms/cm3, or is free of n-type dopant atoms.

### Claim 12 (depends on 9)

The three-dimensional memory device of claim 9, wherein:
the pedestal channel portion comprises polysilicon containing arsenic atoms at an average atomic concentration in a range from 1.0×1018 atoms/cm3 to 1.0×1020 atoms/cm3; and
the vertical semiconductor channel comprises arsenic atoms at an average atomic concentration less than 1.0×1017 atoms/cm3 or is free of arsenic atoms.

### Claim 13 (depends on 9)

The three-dimensional memory device of claim 9, wherein:
the pedestal channel portion is polycrystalline and has a first average grain size; and
the vertical semiconductor channel is polycrystalline and has a second average grain size that is at least 50% larger than the first average grain size.

### Claim 14

A method of forming a three-dimensional memory device, comprising:
forming a source-level sacrificial layer over a substrate;
forming an alternating stack of insulating layers and sacrificial layers containing a memory opening therethrough over the source-level sacrificial layer, wherein the memory opening has a width-modulated vertical cross-sectional profile that has a first width at a lower region extending through the source-level sacrificial layer and a first subset of layers of the alternating stack, and has a second width that is greater than the first width at a middle region located at levels of a second subset of the layers of the alternating stack that overlie the first subset of the layers of the alternating stack;
forming a memory film at a peripheral portion of the memory opening;
forming a pedestal channel portion in the lower region of the memory opening by conformally depositing a first semiconductor material over the memory film and plugging the lower region of the memory opening with the first semiconductor material, and by isotropically etching the first semiconductor material from the middle region of the memory opening;
forming a vertical semiconductor channel in the middle region of the memory opening over the pedestal channel portion and the memory film by conformally depositing a second semiconductor material;
forming a source cavity by removing the source-level sacrificial layer and a cylindrical portion of the memory film located at a level of the source-level sacrificial layer;
depositing a source contact layer in the source cavity on a cylindrical sidewall of the pedestal channel portion; and
replacing the sacrificial material layers with electrically conductive layers.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
depositing a first layer stack including the first subset of the layers of the alternating stack and the second subset of the layers of the alternating stack over the substrate;
forming a first opening having the first width through the first layer stack; and
expanding an upper region of the first opening to the second width by performing an isotropic etch process while an etch stop fill material portion fills a lower region of the first opening,
wherein forming the memory opening comprises removing the etch stop fill material portion.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
depositing a second layer stack including a third subset of the layers of the alternating stack over the second layer stack; and
forming a second opening having a third width through the second layer stack,
wherein:
the third width is less than the second width and is greater than the first width; and
the continuous void includes an entire volume of the second opening.

### Claim 17 (depends on 14)

The method of claim 14, wherein:
the first semiconductor material comprises polysilicon deposited with in-situ doping of carbon atoms; and
the second semiconductor material comprises polysilicon deposited without in-situ doping of carbon atoms.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the pedestal channel portion is polycrystalline and has a first average grain size; and
the vertical semiconductor channel is polycrystalline and has a second average grain size that is at least 50% greater than the first average grain size.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the source contact layer is deposited with in-situ doping of n-type dopant atoms; and
the n-type dopant atoms in the source contact layer diffuse in the pedestal channel portion at a lower diffusion rate than in the vertical semiconductor channel.

### Claim 20 (depends on 14)

The method of claim 14, wherein:
the first semiconductor material is deposited with in-situ doping of arsenic atoms; and
the second semiconductor material is deposited without in-situ doping of any n-type dopant atoms.