# US 2022/0045090 A1 · Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same

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- Number: US 2022/0045090 A1
- Document ID: US20220045090A1
- Status: Published application
- Kind: A1
- Application number: 16/985,340
- Filed: 2020-08-05
- Published: 2022-02-10
- Earliest claimed: 2020-08-05
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Zhixin Cui; Satoshi Shimizu; Yanli Zhang
- Web page: https://patentgrep.com/patent/US20220045090A1

## CPC

- H10B 41/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 8/14: Word line organisation; Word line lay-out
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/42: Vias, e.g. via plugs
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
a source contact layer located between the substrate and the alternating stack;
a memory opening vertically extending through the alternating stack and the source contact layer; and
a memory opening fill structure located within the memory opening and comprising a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel, wherein the composite semiconductor channel comprises:
a pedestal channel portion having a cylindrical sidewall segment that contacts the source contact layer and including at least one of carbon or arsenic dopant atoms at a first average dopant concentration; and
a vertical semiconductor channel contacting a top surface of the pedestal channel portion, wherein the vertical semiconductor channel includes the at least one of carbon or arsenic dopant atoms at a second average dopant concentration that is less than 20% of the first average dopant concentration or is free of the at least one of carbon or arsenic dopants atoms.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the memory film comprises a concave annular bottom surface segment that contacts the source contact layer; and
an outer periphery of the concave annular bottom surface is located at a greater vertical distance from the substrate than an inner periphery of the concave annular bottom surface is from the substrate.

### Claim 3 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
an upper source-level semiconductor layer is located between the source contact layer and the alternating stack;
the electrically conductive layers comprise:
source-select-level electrically conductive layers located below a horizontal plane including an outer periphery of the top surface of the pedestal channel portion, and
word-line-level electrically conductive layers located above the horizontal plane including the outer periphery of the top surface of the pedestal channel portion; and
the memory opening vertically extends through the source-select-level electrically conductive layers, the word-line-level electrically conductive layers, and the upper source-level semiconductor layer with a straight sidewall.

### Claim 4 (depends on 1)

The three-dimensional memory device of claim 1, wherein the pedestal channel portion contacts the source contact layer at a cylindrical interface located within a cylindrical vertical plane located at or inside an inner sidewall of the memory film.

### Claim 5 (depends on 1)

The three-dimensional memory device of claim 1, wherein the memory opening fill structure comprises a bottom dielectric cap structure having a same set of material compositions as component layers of the memory film, and underlying the pedestal channel portion.

### Claim 6 (depends on 5)

The three-dimensional memory device of claim 5, wherein the bottom dielectric cap structure comprises a concave annular surface that contacts the source contact layer.

### Claim 7 (depends on 5)

The three-dimensional memory device of claim 5, wherein a bottom periphery of an outer sidewall of the memory film and a top periphery of an outer sidewall of the bottom dielectric cap structure have a same horizontal cross-sectional shape and overlap with each other in a plan view.

### Claim 8 (depends on 5)

The three-dimensional memory device of claim 5, wherein the memory opening fill structure comprises a void that is free of any solid phase material between the bottom dielectric cap structure and the pedestal channel portion.

### Claim 9 (depends on 9)

The three-dimensional memory device of claim 9, wherein:
the void comprises a tapered concave upper boundary at an interface with a tapered convex bottom surface of the pedestal channel portion; and
the void has a greater height at a center portion than at a peripheral portion that laterally surrounds the center portion.

### Claim 10 (depends on 5)

The three-dimensional memory device of claim 5, wherein each of the memory film and the bottom dielectric cap structure comprises a layer stack including, from one side to another, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.

### Claim 11 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the pedestal channel portion comprises polysilicon containing carbon atoms at an average atomic concentration in a range from 5.0×1017 atoms/cm3 to 2.0×1021 atoms/cm3; and
the vertical semiconductor channel comprises polysilicon containing carbon atoms at an average atomic concentration less than 1.0×1017 atoms/cm3 or is free of carbon atoms.

### Claim 12 (depends on 11)

The three-dimensional memory device of claim 11, wherein:
the pedestal channel portion comprises n-type dopant atoms at an average atomic concentration in a range from 1.0×1018 atoms/cm3 to 1.0×1020 atoms/cm3; and
the vertical semiconductor channel includes n-type dopant atoms at an average atomic concentration of than 1.0×1017 atoms/cm3, or is free of n-type dopant atoms.

### Claim 13 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the pedestal channel portion comprises polysilicon containing arsenic atoms at an average atomic concentration in a range from 1.0×1018 atoms/cm3 to 1.0×1020 atoms/cm3; and
the vertical semiconductor channel comprises polysilicon containing arsenic atoms at an average atomic concentration less than 1.0×1017 atoms/cm3 or is free of arsenic atoms.

### Claim 14 (depends on 1)

The three-dimensional memory device of claim 1, wherein:
the pedestal channel portion is polycrystalline and has a first average grain size; and
the vertical semiconductor channel is polycrystalline and has a second average grain size that is at least 50% larger than the first average grain size.

### Claim 15

A method of forming a three-dimensional semiconductor device, comprising:
forming a source-level sacrificial layer over a substrate;
forming an alternating stack of insulating layers and sacrificial material layers over the sacrificial source layer;
forming a memory opening through the alternating stack and the source-level sacrificial layer;
forming an in-process memory opening fill structure comprising a memory film and a sacrificial memory opening fill material portion in the memory opening;
forming a source cavity by removing the source-level sacrificial layer and a cylindrical portion of the memory film located at a level of the source-level sacrificial layer;
depositing a source contact layer in the source cavity on a cylindrical sidewall of the sacrificial memory opening fill material portion;
forming a memory cavity by removing the sacrificial memory opening fill material portion;
forming a pedestal channel portion by selectively growing a first semiconductor material from a surface of the source contact layer in a lower portion of the memory cavity;
forming a vertical semiconductor channel by non-selectively depositing a second semiconductor material over the pedestal channel portion and on the memory film; and
replacing the sacrificial material layers with electrically conductive layers.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the first semiconductor material comprises polysilicon deposited with in-situ doping of carbon atoms; and
the second semiconductor material comprises polysilicon deposited without in-situ doping of carbon atoms.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the pedestal channel portion has a first average grain size; and
the vertical semiconductor channel has a second average grain size that is at least 50% larger than the first average grain size.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the source contact layer is deposited with in-situ doping of n-type dopant atoms; and
the n-type dopant atoms in the source contact layer diffuse in the pedestal channel portion at a lower diffusion rate than in the vertical semiconductor channel.

### Claim 19 (depends on 15)

The method of claim 15, wherein:
the first semiconductor material is deposited with in-situ doping of arsenic atoms; and
the second semiconductor material is deposited without in-situ doping of any n-type dopant atoms.

### Claim 20 (depends on 15)

The method of claim 15, wherein:
the surface of the source contact layer from which the first semiconductor material grows selectively comprises a cylindrical surface;
the first semiconductor material is selectively grown by performing a selective semiconductor deposition process in which a semiconductor precursor gas and an etchant gas are concurrently or alternately flown into a process chamber in which the substrate is disposed;
the first semiconductor material does not grow from surfaces of the memory film during the selective semiconductor deposition process; and
a void that is free of any solid phase material is formed at a bottom portion of the memory opening underneath the pedestal channel portion.