# US 2022/0045089 A1 · Three-dimensional memory device with double-sided stepped surfaces and method of making thereof

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- Number: US 2022/0045089 A1
- Document ID: US20220045089A1
- Status: Published application
- Kind: A1
- Application number: 16/985,305
- Filed: 2020-08-05
- Published: 2022-02-10
- Earliest claimed: 2020-08-05
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Yuki MIZUTANI; Masaaki HIGASHITANI
- Web page: https://patentgrep.com/patent/US20220045089A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10B 43/40: characterised by the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.

## Claims

### Claim 1

A semiconductor structure comprising a memory die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
memory stack structures vertically extending through the alternating stack, wherein:
the alternating stack comprises a first layer stack including first insulating layers and first electrically conductive layers and a second layer stack including second insulating layers and second electrically conductive layers and vertically spaced from the substrate by the first alternating stack;
the first layer stack comprises a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces; and
the second layer stack comprises a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the memory die further comprises:
an upright-stepped dielectric material portion contacting the first stepped surfaces and having a first variable horizontal-cross-sectional area that decreases with the vertical distance from the substrate; and
a retro-stepped dielectric material portion contacting the second stepped surfaces having a second variable horizontal-cross-sectional area that increases with the vertical distance from the substrate.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the memory die further comprises:
substrate-side contact via structures vertically extending through the upright-stepped dielectric material portion and contacting a proximal surface of a respective one of the first electrically conductive layers; and
interconnect-side contact via structures vertically extending through the retro-stepped dielectric material portion and contacting a distal surface of a respective one of the second electrically conductive layers.

### Claim 4 (depends on 3)

The three dimensional memory device of claim 3, wherein:
the substrate comprises a semiconductor material layer having a front surface in contact with a proximal planar surface of the alternating stack and a backside surface located on an opposite side of the front surface; and
the memory die comprises a contact-level dielectric layer located on a distal planar surface of the alternating stack.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein substrate-side end surfaces of the substrate-side contact via structures are located within a horizontal plane including a planar surface of the upright-stepped dielectric material portion.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein:
a backside surface of the semiconductor material layer is located within the horizontal plane including the planar surface of the upright-stepped dielectric material portion; and
a sidewall of the upright-stepped dielectric material portion contacts the semiconductor material layer.

### Claim 7 (depends on 4)

The semiconductor structure of claim 4, wherein interconnect-side end surfaces of the interconnect-side contact via structures are located within a horizontal plane including a distal surface of the contact-level dielectric layer.

### Claim 8 (depends on 4)

The semiconductor structure of claim 4, wherein the memory die further comprises:
laterally-isolated through-stack connection via structures comprising a respective combination of a connection via structure and a tubular dielectric spacer and vertically extending through each layer within the alternating stack; and
substrate-side metal interconnect structures electrically connecting a respective pair of one of the substrate-side contact via structures and one of the connection via structures.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein each of the substrate-side metal interconnect structures comprises a source-side metal line contacting a planar surface of the upright-stepped dielectric material portion, and wherein each memory stack structure comprises a vertical semiconductor channel and a memory film.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the memory die further comprises a backside insulating layer contacting a backside surface of the semiconductor material layer and the planar surface of the upright-stepped dielectric material portion and embedding the substrate-side metal interconnect structures.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein:
the laterally-isolated through-stack connection via structures vertically extend through the contact-level dielectric layer and the upright-stepped dielectric material portion;
source-side end surfaces of the laterally-isolated through-stack connection via structures are located within a horizontal plane including substrate-side end surfaces of the substrate-side contact via structures; and
interconnect-side end surfaces of the laterally-isolated through-stack connection via structures are located within a horizontal plane including interconnect-side end surfaces of the interconnect-side contact via structures.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the memory die further comprises interconnect-level dielectric layers embedding metal interconnect structures and located on an opposite side of the substrate with respect to the alternating stack, wherein the metal interconnect structures are electrically connected to the electrically conductive layers.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, further comprising a logic die comprising a logic circuit configured to control operation of memory elements within the memory stack structures, and comprising logic-side dielectric material layers embedding logic-side metal interconnect structures and logic-side metal bonding pads, wherein:
the memory die comprises memory-side metal bonding pads embedded in the interconnect-level dielectric layers and electrically connected to the metal interconnect structures; and
the logic die is bonded to the memory die through metal-to-metal bonding between the logic-side metal bonding pads and the memory-side metal bonding pads.

### Claim 14

A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate comprising a semiconductor material layer, the alternating stack comprising a first layer stack of first insulating layers and first spacer material layers and a second layer stack of second insulating layers and second spacer material layers that is more distal from the substrate than the first layer stack is from the substrate, and the first spacer material layers and the second spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers and second electrically conductive layers, respectively;
forming distal stepped surfaces by patterning the second layer stack, wherein lateral extents of the second spacer material layers decrease with a vertical distance from the substrate upon formation of the distal stepped surfaces;
forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film;
forming an opening through the semiconductor material layer;
forming proximal stepped surfaces by patterning a portion of the first layer stack located within an area of the opening through the semiconductor material layer employing a plurality of masked anisotropic etch processes that etches unmasked regions of the portion of the first layer stack along a direction that points from the substrate toward the alternating stack; and
forming an upright-stepped dielectric material portion on the proximal stepped surfaces of the first layer stack.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming substrate-side contact via structures through the upright-stepped dielectric material portion on a proximal surface of a respective one of the first electrically conductive layers.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a retro-stepped dielectric material portion on the distal stepped surfaces, wherein the retro-stepped dielectric material portion has a variable horizontal cross-sectional area that increases with a vertical distance from the substrate; and
forming interconnect-side contact via structures through the retro-stepped dielectric material portion on a distal surface of a respective one of the second electrically conductive layers after formation of the substrate-side contact via structures.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming a contact-level dielectric layer over the alternating stack after formation of the memory stack structures;
attaching a carrier substrate to the contact-level dielectric layer; and
thinning the semiconductor material layer from a backside,
wherein the opening through the semiconductor material layer is formed after thinning the semiconductor material layer, wherein a first portion of a proximal surface of the alternating stack located within an area of the opening is physically exposed and a second portion of the proximal surface of the alternating stack located outside the area of the opening contacts the semiconductor material layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a patterned hard mask layer over the first portion of the proximal surface of the alternating stack, a sidewall of the semiconductor material layer, and a backside surface of the semiconductor layer, wherein the patterned hard mask layer has an opening within a region of the first portion of the proximal surface of the alternating stack;
forming a trimmable etch mask layer including an edge that extends across the opening in the patterned hard mask layer; and
performing the plurality of masked anisotropic etch processes, wherein the trimmable etch mask layer is employed as an etch mask for each of the masked anisotropic etch processes, and the trimmable etch mask layer is trimmed between each sequentially neighboring pair of masked anisotropic etch processes.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
forming laterally-isolated through-stack connection via structures comprising a respective combination of a connection via structure and a tubular dielectric spacer through a portion of the alternating stack in which each layer of the alternating stack is present; and
forming substrate-side metal interconnect structures on the substrate-side contact via structures, wherein each of the connection via structures contacts a respective one of the substrate-side metal interconnect structures.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
forming interconnect-level dielectric layers embedding metal interconnect structures over the alternating stack, wherein the metal interconnect structures are electrically connected to the electrically conductive layers;
forming memory-side metal bonding pads embedded in the interconnect-level dielectric layers and electrically connected to the metal interconnect structures;
providing a logic die comprising a logic circuit configured to control operation of memory elements within the memory stack structures, and comprising logic-side dielectric material layers embedding logic-side metal interconnect structures and logic-side metal bonding pads; and
bonding the logic die to the memory die through metal-to-metal bonding between the logic-side metal bonding pads and the memory-side metal bonding pads.