# US 2022/0045087 A1 · Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same

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- Number: US 2022/0045087 A1
- Document ID: US20220045087A1
- Status: Published application
- Kind: A1
- Application number: 16/984,920
- Filed: 2020-08-04
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Ashish BARASKAR; Raghuveer S. MAKALA; Peter RABKIN
- Web page: https://patentgrep.com/patent/US20220045087A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 64/031: {of data-storage electrodes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

## Claims

### Claim 1

A memory device comprising:
a strained single-crystalline silicon layer;
an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer, a vertical semiconductor channel, a vertical stack of memory elements located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers, and a drain region.

### Claim 2 (depends on 1)

The memory device of claim 1, further comprising a single-crystalline silicon-germanium compound semiconductor layer, wherein the strained single-crystalline silicon layer is located on and in epitaxial alignment with the single-crystalline silicon-germanium compound semiconductor layer.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein:
the strained single-crystalline silicon layer and the epitaxial silicon-containing pedestal channel portion have a doping of a first conductivity type; and
a source region having a doping of a second conductivity type opposite to the first conductivity type is in contact with the strained single-crystalline silicon layer and is located outside the memory opening.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the source region comprises:
a lower source portion comprising a doped single-crystalline silicon-germanium compound semiconductor material having a doping of the second conductivity type; and
an upper source portion comprising a doped single-crystalline strained silicon material and having a doping of the second conductivity type.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a doping of the first conductivity type or is intrinsic;
the vertical semiconductor channel is intrinsic or has a doping of the first conductivity type; and
the drain region comprises a semiconductor material having a doping of the second conductivity type.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein:
the single-crystalline silicon-germanium compound semiconductor layer comprises a compositionally graded single-crystalline silicon-germanium compound semiconductor material in which an atomic percentage of germanium increases monotonically with a vertical distance from the substrate single-crystalline silicon layer;
an atomic percentage of germanium in the single-crystalline silicon-germanium compound semiconductor layer is in a range from 10% to 80%; and
the strained single-crystalline silicon layer is free of germanium or includes germanium atoms at an atomic percentage less than 0.1%.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a variable in-plane lattice constant that increases monotonically with a vertical distance from the substrate single-crystalline silicon layer; and
a dislocation density decreases with the vertical distance from the substrate single-crystalline silicon layer within an upper region of the single-crystalline silicon-germanium compound semiconductor layer.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a first thickness;
the strained single-crystalline silicon layer has a second thickness; and
a ratio of the second thickness to the first thickness is in a range from 1:1000 to 1:10.

### Claim 9 (depends on 2)

The memory device of claim 2, wherein the single-crystalline silicon-germanium compound semiconductor layer is formed on a single-crystalline silicon substrate.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the drain region comprises:
a semiconductor drain portion including a doped silicon-containing semiconductor material and contacting an end portion of the vertical semiconductor channel; and
a nickel-aluminum-semiconductor alloy drain portion comprising silicon.

### Claim 11 (depends on 10)

The memory device of claim 10, further comprising a metallic drain electrode comprising an elemental metal or a conductive metallic nitride material in contact with a top surface of the nickel-aluminum-semiconductor alloy drain portion.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the epitaxial silicon-containing pedestal channel portion comprises single-crystalline silicon or single-crystalline silicon-germanium compound semiconductor layer.

### Claim 13 (depends on 1)

The memory device of claim 1, wherein:
the memory opening fill structure comprises a memory film including a layer stack containing at least a charge storage layer and a tunneling dielectric layer; and
the vertical stack of memory elements comprises portions of the charge storage layer located at levels of the electrically conductive layers.

### Claim 14

A method of forming a memory device, comprising:
epitaxially growing a single-crystalline silicon-germanium compound semiconductor layer on a substrate single-crystalline silicon layer;
epitaxially growing a strained single-crystalline silicon layer in epitaxial alignment with the single-crystalline silicon-germanium compound semiconductor layer;
forming an alternating stack of insulating layers and spacer material layers over the strained single-crystalline silicon layer, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming a memory opening through the alternating stack, wherein a top surface of the strained single-crystalline silicon layer is physically exposed;
epitaxially growing an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer at a bottom portion of the memory opening;
forming a vertical stack of memory elements at a periphery of the memory opening at levels of the spacer material layers that overlie a top surface of the epitaxial silicon-containing pedestal channel portion; and
forming a vertical semiconductor channel and a drain region in remaining volumes of the memory opening.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the single-crystalline silicon-germanium compound semiconductor layer comprises a compositionally graded single-crystalline silicon-germanium compound semiconductor material in which an atomic percentage of germanium increases monotonically with a vertical distance from the substrate single-crystalline silicon layer; and
an atomic percentage of germanium in the single-crystalline silicon-germanium compound semiconductor layer is in a range from 10% to 80%,
wherein the strained single-crystalline silicon layer is free of germanium or includes germanium atoms at an atomic percentage less than 0.1%.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
the single-crystalline silicon-germanium compound semiconductor layer is grown with a vertical compositional modulation such that an in-plane lattice constant of the single-crystalline silicon-germanium compound semiconductor layer increases monotonically with a vertical distance from the substrate single-crystalline silicon layer; and
the single-crystalline silicon-germanium compound semiconductor layer is grown to a first thickness such that a dislocation density decreases with the vertical distance from the substrate single-crystalline silicon layer within an upper region of the single-crystalline silicon-germanium compound semiconductor layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein:
the strained single-crystalline silicon layer and the epitaxial silicon-containing pedestal channel portion are grown with a doping of a first conductivity type; and
the method further comprises forming a source region having a doping of a second conductivity type by implanting a portion of the strained single-crystalline material layer and an underlying portion of the single-crystalline silicon-germanium compound semiconductor layer that are located outside the memory opening with dopants of the second conductivity type opposite to the first conductivity type.

### Claim 18 (depends on 14)

The method of claim 14, wherein the spacer material layers are formed as sacrificial material layers, and the method further comprises:
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the epitaxial silicon-containing pedestal channel portion;
forming a tubular dielectric spacer by oxidizing a cylindrical surface portion of the epitaxial silicon-containing pedestal channel portion; and
forming the electrically conductive layers in the backside recesses, wherein a bottommost one of the electrically conductive layers is formed around the tubular dielectric spacer.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the drain region comprises:
forming a semiconductor drain portion including a doped silicon-containing semiconductor material and on an end portion of the vertical semiconductor channel; and
forming a nickel-aluminum-semiconductor alloy drain portion comprising silicon by reacting a surface region of the semiconductor drain portion with a nickel-aluminum-containing material.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
forming a memory film including a layer stack containing at least a charge storage layer and a tunneling dielectric layer at a periphery of the memory opening over a top surface of an epitaxial silicon-containing pedestal channel portion;
forming an opening at a bottom portion of the memory film by performing an anisotropic etch process; and
forming the vertical semiconductor channel by conformally depositing a semiconductor material on an inner sidewall of the memory film and on a physically exposed surface of the epitaxial silicon-containing pedestal channel portion, wherein the vertical stack of memory elements comprises portions of the charge storage layer located at levels of the electrically conductive layers.