# US 2022/0045083 A1 · Semiconductor device and electronic system

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- Number: US 2022/0045083 A1
- Document ID: US20220045083A1
- Status: Published application
- Kind: A1
- Application number: 17/204,248
- Filed: 2021-03-17
- Published: 2022-02-10
- Earliest claimed: 2020-08-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: JAERYONG SIM; SHINHWAN KANG; JEEHOON HAN
- Web page: https://patentgrep.com/patent/US20220045083A1

## CPC

- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

## Claims

### Claim 1

A semiconductor device, comprising:
a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure;
a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers disposed in a gate region of the stack structure and first insulating horizontal layers disposed in a first insulating region of the stack structure;
a memory vertical structure including a portion penetrating the gate horizontal layers in a vertical direction;
dummy vertical structures including a portion penetrating the gate horizontal layers in the vertical direction and spaced apart from the memory vertical structure;
a first peripheral contact plug including a portion penetrating the first insulating region in the vertical direction; and
gate contact plugs disposed on gate pads of the gate horizontal layers,
wherein the gate contact plugs and the first peripheral contact plugs have upper surfaces disposed at the same level,
the memory vertical structure includes a first material different from a material of the dummy vertical structures,
the memory vertical structure and the dummy vertical structure contact the pattern structure, and
at least one of the dummy vertical structures extends further downwardly into the pattern structure than the memory vertical structure from the upper surface of the pattern structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the lower structure further includes a pad pattern in the lower insulating structure and a gap-fill insulating layer penetrating the pattern structure and overlapping the pad pattern, and
the first peripheral contact plug extends downwardly from a portion penetrating the first insulating region to penetrate the gap-fill insulating layer and contact the pad pattern.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the lower insulating structure includes a first lower insulating layer at least partially surrounding a side surface of the pad pattern, an etch stop layer on the first lower insulating layer and the pad pattern, and a second lower insulating layer on the etch stop layer,
the etch stop layer includes a material different from a material of the second lower insulating layer,
a thickness of the etch stop layer is less than a thickness of the second lower insulating layer, and
a portion of the first peripheral contact plug penetrates the second lower insulating layer and the etch stop layer to contact the pad pattern.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first peripheral contact plug extends further downwardly from the upper surface of the pad pattern into the pad pattern, and
a vertical height of the first peripheral contact plug extending from the upper surface of the pad pattern into the pad pattern is greater than a thickness of the etch stop layer.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising:
an insulating contact spacer layer covering at least a portion of a side surface of the first peripheral contact plug,
wherein the insulating contact spacer layer contacts the pad pattern, and
a lower end of the insulating contact spacer layer is at a higher level than a lower end of the first peripheral contact plug.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
at least a portion of a side surface of the memory vertical structure includes a bent portion at a level between an uppermost gate horizontal layer of the gate horizontal layers of the lower stack structure and a lowermost gate horizontal layer of the gate horizontal layers of the upper stack structure,
the memory vertical structure includes an insulating core pattern, a channel layer covering a side surface and a bottom surface of the insulating core pattern, and a data storage structure disposed on an external surface of the channel layer, and
the first material of the memory vertical structure is a material of the channel layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion,
the upper plug portion has a width greater than a width of the lower plug portion, and
in the first peripheral contact plug, a side surface of the lower plug portion is bent in a direction away from a central axis of the lower plug portion and extends to a side surface of the upper plug portion.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the upper plug portion includes a portion contacting the lower plug portion and a portion overlapping the first insulating horizontal layers.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein a first central axis of the lower plug portion and a second central axis of the upper plug portion are misaligned.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the lower structure further includes a pad pattern, a buffer pad pattern disposed on the pad pattern, and a gap-fill insulating layer disposed on the buffer pad pattern and penetrating the pattern structure,
an upper surface of the buffer pad pattern is at a same level of at least one of a level of the upper surface of the lower insulating structure, and a level higher than a level of the lower surface of the pattern structure,
the first peripheral contact plug extends downwardly from a portion penetrating the first insulating region to contact the buffer pad pattern, and
a portion of the first peripheral contact plug extends into the buffer pad pattern.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
a bit line electrically connected to the memory vertical structure on the memory vertical structure; and
a gate connection wiring electrically connected to the first peripheral contact plug and one of the gate contact plugs on the gate contact plugs and the first peripheral contact plug.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulating contact spacer layer disposed on at least a portion of a side surface of the first peripheral contact plug, and
the insulating contact spacer layer includes a spacer portion interposed between the first peripheral contact plug and the first insulating horizontal layers.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first peripheral contact plug has a first plug side surface and a second plug side surface opposing the first plug side,
at least one of the first insulating horizontal layers includes a first horizontal portion facing the first plug side surface and a second horizontal portion facing the second plug side surface,
the insulating contact spacer layer includes a first spacer portion interposed between the first plug side surface and the first horizontal portion and a second spacer portion interposed between the second plug side surface and the second horizontal portion, and
a thickness of the first spacer portion is greater than a thickness of the second spacer portion.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second peripheral contact plug,
wherein the stack structure further includes a second insulating region spaced apart from the first insulating region,
the horizontal layers further include second insulating horizontal layers disposed in the second insulating region,
the second peripheral contact plug includes a portion penetrating the second insulating region in the vertical direction, and
an uppermost first insulating horizontal layer of the first insulating horizontal layers is disposed at a level different from a level of an uppermost second insulating horizontal layer of the second insulating horizontal layers.

### Claim 15

A semiconductor device, comprising:
a lower structure including a peripheral circuit and a pad pattern electrically connected to the peripheral circuit;
a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, where the stack structure extends from a memory cell array region to a staircase region adjacent to the memory cell array region, the stack structure includes a gate region and an insulating region, and a side surface of the insulating region is at least partially surrounded by the gate region in the staircase region, and the horizontal layers include gate horizontal layers disposed in the gate region and insulating horizontal layers disposed in the insulating region;
a memory vertical structure including a portion penetrating the gate horizontal layers in a vertical direction in the memory cell array region;
dummy vertical structures including a portion penetrating the gate horizontal layers in the vertical direction in the staircase region;
a peripheral contact plug contacting the pad pattern, extending in the vertical direction, and penetrating the insulating region; and
gate contact plugs disposed on the gate pads of the gate horizontal layers in the staircase region,
wherein the gate contact plugs and the peripheral contact plugs have upper surfaces disposed at the same level,
the stack structure includes a first staircase region and a second staircase region arranged in a first direction away from the memory cell array region, and a staircase connection region disposed between the first staircase region and the second staircase region in the staircase region,
each of the first and second staircase regions includes a staircase shape extending downwardly by a first height difference in the first direction,
an upper surface of the staircase connection region has a shape that is at least one of flattened in the first direction, and having a height difference less than the first height difference in the first direction,
a portion of the staircase connection region is an insulating region, and
the memory vertical structure includes a material different from a material of the dummy vertical structures.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising:
an insulating contact spacer layer covering at least a portion of a side surface of the peripheral contact plug,
wherein the insulating contact spacer layer contacts the pad pattern, and
a lower end of the insulating contact spacer layer is at a higher level than a lower end of the peripheral contact plug.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion,
the upper plug portion has a width greater than a width of the lower plug portion, and
a first central axis of the lower plug portion and a second central axis of the upper plug portion are misaligned.

### Claim 18

An electronic system, comprising a main substrate, a semiconductor device on the main substrate and a controller electrically connected to the semiconductor device on the main substrate,
wherein the semiconductor device includes:
a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure;
a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers disposed in the gate region of the stack structure and insulating horizontal layers disposed in the insulating region of the stack structure;
a memory vertical structure including a portion penetrating the gate horizontal layers in a vertical direction;
dummy vertical structures including a portion penetrating the gate horizontal layers in the vertical direction and spaced apart from the memory vertical structure;
a peripheral contact plug including a portion penetrating the insulating region in the vertical direction; and
gate contact plugs disposed on gate pads of the gate horizontal layers,
wherein the gate contact plugs and the peripheral contact plugs have upper surfaces disposed at the same level,
each of the dummy vertical structures has a width greater than a width of each of the memory vertical structures at the same level,
the memory vertical structure includes a material different from a material of the dummy vertical structures,
the memory vertical structure and the dummy vertical structure extend downwardly from an upper surface of the pattern structure into the pattern structure to contact the pattern structure, and
at least one of the dummy vertical structures extends downwardly further into the pattern structure than the memory vertical structure from the upper surface of the pattern structure.

### Claim 19 (depends on 18)

The electronic system of claim 18, further comprising:
an insulating contact spacer layer covering at least a portion of a side surface of the peripheral contact plug,
wherein the lower insulating structure further includes a pad pattern,
the pattern structure further includes a silicon layer,
the insulating contact spacer layer contacts the pad pattern, and
a lower end of the insulating contact spacer layer is at a higher level than a lower end of the peripheral contact plug.

### Claim 20 (depends on 18)

The electronic system of claim 18, wherein the peripheral contact plug includes a lower plug portion and an upper plug portion on the lower plug portion,
the upper plug portion has a width greater than a width of the lower plug portion, and
a first central axis of the lower plug portion and a second central axis of the upper plug portion are misaligned.