# US 2022/0045081 A1 · Nonvolatile memory device and method for fabricating the same

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- Number: US 2022/0045081 A1
- Document ID: US20220045081A1
- Status: Published application
- Kind: A1
- Application number: 17/507,989
- Filed: 2021-10-22
- Published: 2022-02-10
- Earliest claimed: 2018-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Hoon JANG; Woo Sung YANG; Joon Sung LIM; Sung Min HWANG
- Web page: https://patentgrep.com/patent/US20220045081A1

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a substrate including a cell region and a peripheral circuit region;
a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially;
a semiconductor pattern connected to the substrate through the stacked structure;
a peripheral circuit element on the peripheral circuit region;
a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element; and
a lower contact connected to the peripheral circuit element through the first interlayer insulating film,
a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, further comprising:
a second interlayer insulating film covering the stacked structure and the first interlayer insulating film; and
an upper contact connected to the lower contact through the second interlayer insulating film.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein a width of the lower contact is larger than a width of the upper contact at the same level as a top surface of the first interlayer insulating film.

### Claim 4 (depends on 2)

The nonvolatile memory device of claim 2, wherein the lower contact and the upper contact include different materials from each other.

### Claim 5 (depends on 2)

The nonvolatile memory device of claim 2, wherein a bottom surface of the upper contact is lower than an uppermost surface of the lower contact.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first interlayer insulating film covers the lowermost gate pattern of the plurality of gate patterns.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the lowermost gate pattern of the plurality of gate patterns extends along a top surface of the first interlayer insulating film.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein the height of the top surface of the lower contact is substantially equal to a height of a top surface of the first interlayer insulating film.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the lower contact includes a first portion directly connected to the peripheral circuit element and a second portion on the first portion, and
a width of a lowermost portion of the second portion is larger than a width of an uppermost portion of the first portion at a boundary between the first portion and the second portion.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the lower contact includes a first portion directly connected to the peripheral circuit element and a second portion on the first portion, and
with respect to a top surface of the substrate, a slope of a sidewall of the second portion is smaller than a slope of a sidewall of the first portion.

### Claim 11

A nonvolatile memory device comprising:
a substrate including a cell region and a peripheral circuit region;
a stacked structure on the cell region, the stacked structure including a ground selection line, a plurality of word lines and a string selection line stacked sequentially from a top surface of the substrate, a lowermost word line of the plurality of word lines being adjacent to the ground selection line;
a peripheral circuit element on the peripheral circuit region;
a semiconductor pattern penetrating through the stacked structure;
a peripheral circuit contact including a lower contact and an upper contact, the lower contact being connected to the peripheral circuit element, and the upper contact being connected to the lower contact on the lower contact; and
a first cell contact connected to the ground selection line,
wherein a height of a top surface of the lower contact being higher than a top surface of the ground selection line, and being lower than or equal to a height of a bottom surface of the lowermost word line of the plurality of word lines, the upper contact has a bottom surface below the top surface of the lower contact and the bottom surface of the upper contact is within the lower contact, and
wherein a bottom surface of the first cell contact is below the top surface of the lower contact and in direct contact with the ground selection line.

### Claim 12 (depends on 11)

The nonvolatile memory device of claim 11, further comprising a plurality of second cell contacts connected to the plurality of word lines.

### Claim 13 (depends on 12)

The nonvolatile memory device of claim 12, wherein the upper contact, the first cell contact and the plurality of second cell contacts have substantially the same material composition.

### Claim 14 (depends on 11)

The nonvolatile memory device of claim 11, further comprising a sacrificial pattern extending along a profile of a top surface of the peripheral circuit element,
wherein the lower contact is connected to the peripheral circuit element through the sacrificial pattern.

### Claim 15 (depends on 14)

The nonvolatile memory device of claim 14, wherein a thickness of the sacrificial pattern is substantially equal to a thickness of the ground selection line.

### Claim 16

A nonvolatile memory device comprising:
a substrate including a cell region and a peripheral circuit region;
a stacked structure on the cell region, the stacked structure including a ground selection line, a plurality of word lines and a string selection line stacked sequentially from a top surface of the substrate, the plurality of word lines including a first word line being a lowermost word line of the plurality of word lines and being adjacent to the ground selection line;
a semiconductor pattern penetrating through the stacked structure;
a peripheral circuit element on the peripheral circuit region;
an interlayer insulating film covering the stacked structure and the peripheral circuit region on the substrate;
a lower contact connected to the peripheral circuit element in the interlayer insulating film;
an upper contact upper contact being connected to the lower contact on the lower contact; and
a cell contact penetrating through the interlayer insulating film and connected to the ground selection line,
wherein a height of a top surface of the lower contact being higher than a top surface of the ground selection line, and being lower than or equal to a height of a bottom surface of the first word line, the upper contact has a bottom surface below the top surface of the lower contact and the bottom surface of the upper contact is within the lower contact, and
wherein a bottom surface of the cell contact is below the top surface of the lower contact and in direct contact with the ground selection line.

### Claim 17 (depends on 16)

The nonvolatile memory device of claim 16, wherein the plurality of word lines further includes a second word line stacked on the first word line,
a separation distance between the ground selection line and the first word line being greater than a separation distance between the first word line and the second word line.

### Claim 18 (depends on 17)

The nonvolatile memory device of claim 17, wherein the ground selection line, the first word line and the second word line are an initial three gate patterns above the top surface of the substrate.