# US 2022/0045078 A1 · Semiconductor storage device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045078 A1 - Document ID: US20220045078A1 - Status: Published application - Kind: A1 - Application number: 17/190,868 - Filed: 2021-03-03 - Published: 2022-02-10 - Earliest claimed: 2020-08-05 - Applicants: Kioxia Corporation - Inventors: Kazuhito FURUMOTO - Web page: https://patentgrep.com/patent/US20220045078A1 ## CPC - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/30: characterised by the memory core region - H10B 41/30: characterised by the memory core region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A method of manufacturing a semiconductor storage device includes forming a coating layer covering a base layer, forming a recess that penetrates the coating layer and into the base layer, enlarging a portion of the recess to expose a portion of the coating layer in contact with the base layer, and etching a surface of the coating layer exposed inside the recess. ## Claims ### Claim 1 A semiconductor storage device comprising: a base layer; a coating layer covering the base layer; and a columnar body extending into the coating layer and connected to the base layer, wherein, along a longitudinal direction of the columnar body extending from a boundary between the base layer and the coating layer, a cross section of the columnar body perpendicular to the longitudinal direction has a width that becomes smaller for a distance. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein the cross section of the columnar body has a width that becomes smaller from an upper end of the columnar body in a direction towards the boundary between the base layer and the coating layer. ### Claim 3 (depends on 2) The semiconductor storage device according to claim 2, wherein the cross section of the columnar body has a width that continuously becomes smaller from an upper end of the columnar body to some predetermined point, at which the width of the cross section of the columnar body then becomes larger toward the boundary between the base layer and the coating layer. ### Claim 4 (depends on 1) The semiconductor storage device according to claim 1, wherein the coating layer includes a plurality of insulating layers and a plurality of conductor layers that are alternately stacked on the semiconductor layer. ### Claim 5 (depends on 1) The semiconductor storage device according to claim 1, wherein the columnar body has a semiconductor portion and a memory film. ### Claim 6 (depends on 5) The semiconductor storage device according to claim 5, wherein the semiconductor portion occupies a majority of the columnar body and is formed of a material made of amorphous silicon. ### Claim 7 (depends on 5) The semiconductor storage device according to claim 5, the memory film covers the entire side surface of the semiconductor. ### Claim 8 A method of manufacturing a semiconductor storage device comprising: forming a coating layer covering a base layer; forming a recess that penetrates the coating layer and into the base layer; enlarging a portion of the recess to expose a portion of the coating layer in contact with the base layer; and etching a surface of the coating layer exposed inside the recess. ### Claim 9 (depends on 8) The method according to claim 8, wherein the base layer is formed of a material containing silicon. ### Claim 10 (depends on 9) The method according to claim 9, wherein exposing the part of the portion of the coating layer includes enlarging the portion of the recess that is formed in the base layer by etching using a choline aqueous solution. ### Claim 11 (depends on 8) The method according to claim 8, further comprising removing an inner peripheral surface of the recess by removing a portion of the inner peripheral surface of the recess at a lower end portion of the coating layer more than another portion of the coating layer. ### Claim 12 (depends on 11) The method according to claim 11, wherein the inner peripheral surface of the recess is removed by wet etching or Reactive Ion Etching (RIE) using diluted hydrofluoric acid. ### Claim 13 (depends on 11) The method according to claim 11, wherein the inner peripheral surface of the recess is removed so that an inner diameter of the recess in a cross section perpendicular to a longitudinal direction of the recess becomes smaller from an upper side of the coating layer to a lower side of the coating layer. ### Claim 14 (depends on 13) The method according to claim 13, wherein the inner peripheral surface of the recess is removed so that from a cross section of the recess having a smallest inner diameter thereof, the inner diameter of the recess becomes larger toward a lower end of the coating layer in the longitudinal direction. ### Claim 15 (depends on 11) The method according to claim 11, further comprising: after removing the inner peripheral surface of the recess, forming a columnar body in the recess. ### Claim 16 (depends on 15) The method according to claim 15, wherein forming the columnar body in the recess includes: forming a memory film on an inner peripheral surface of the recess; and forming a semiconductor inside the memory film. ### Claim 17 (depends on 11) The method according to claim 11, wherein the coating layer includes a plurality of insulating layers and a plurality of sacrificial layers that are alternately formed, and the method further comprises: replacing the plurality of sacrificial layers with a plurality of conductor layers. ### Claim 18 (depends on 17) The method according to claim 17, wherein replacing the plurality of sacrificial layers with the plurality of conductor layers includes: forming slits so as to divide the entirety of the alternately formed insulating layers and sacrificial layers; removing all of the sacrificial layers by wet etching through the slits; and forming the conductor layers in a space where the sacrificial layers are formed.