# US 2022/0045071 A1 · Semiconductor structure and method for manufacturing semiconductor structure

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- Number: US 2022/0045071 A1
- Document ID: US20220045071A1
- Status: Published application
- Kind: A1
- Application number: 17/445,317
- Filed: 2021-08-18
- Published: 2022-02-10
- Earliest claimed: 2020-08-05
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yachuan HE; Hsin-Pin HUANG
- Web page: https://patentgrep.com/patent/US20220045071A1

## CPC

- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/488: {Word lines}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10P 76/204: {of organic photoresist masks}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
an isolation structure formed in the substrate; and
a word line comprising a first convex portion and a second convex portion, wherein the first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the word line further comprises:
a main body portion, connected with the first convex portion and the second convex portion.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a plurality of first convex portions and a plurality of second convex portions are provided, and the plurality of first convex portions and the plurality of second convex portions are disposed at intervals.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the isolation structure comprises a first isolation structure and a second isolation structure; the first convex portion is located in the first isolation structure, the second convex portion is located in the second isolation structure, and a bottom of the first isolation structure is at lower lever than a bottom of the second isolation structure.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio between the depth of the first convex portion and the depth of the second convex portion is greater than 1.05.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the depth of the first convex portion is greater than 30 nm.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein a length of the first convex portion along a direction perpendicular to an extension direction of the word line is greater than a length of the second convex portion along the direction perpendicular to the extension direction of the word line.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the first convex portion comprises:
a lower convex portion having a side wall with a first slope; and
an upper convex portion having a side wall with a second slope;
wherein the first slope is different from the second slope.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein a side wall of the second convex portion has a third slope and the first slope is equal to the third slope.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the upper convex portion has a section of a circular shape or an elliptical shape along a direction of a surface of the substrate, and the lower convex portion has a section of a strip shape along the direction of the surface of the substrate.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the strip shape comprises two parallel line segments and two arc line segments connecting ends of the two parallel line segments.

### Claim 12 (depends on 4)

The semiconductor structure of claim 4, wherein a plurality of active regions are disposed in the substrate, and the isolation structure is disposed among the plurality of active regions,
wherein the main body portion is intersected with the active regions.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the plurality of active regions are arranged in a plurality of rows,
wherein the first isolation structure is located between ends of two adjacent active regions, and the second isolation structure is located between sides of two adjacent active regions.

### Claim 14

A method for manufacturing a semiconductor structure, comprising:
providing a substrate having an isolation structure and a plurality of active regions, the isolation structure being disposed among the plurality of active regions;
forming a first groove and a second groove at intervals on the isolation structure, wherein a depth of the first groove is greater than a depth of the second groove; and
forming a word line in the substrate, wherein the word line comprises a main body portion, a first convex portion and a second convex portion, and the first convex portion and the second convex portion are respectively disposed in the first groove and the second groove.

### Claim 15 (depends on 14)

The method for manufacturing the semiconductor structure of claim 14, wherein the formation of the first groove and the second groove at intervals on the isolation structure comprises:
forming a groove on the isolation structure, wherein the groove is located between ends of two adjacent active regions; and
forming the first groove and the second groove on the isolation structure having the groove, wherein the first groove is formed at a position where the groove is located.

### Claim 16 (depends on 15)

The method for manufacturing the semiconductor structure of claim 15, wherein the formation of the groove on the isolation structure comprises:
forming a first photoresist layer with a photoresist opening on the substrate, wherein the photoresist opening is located between the ends of two adjacent active regions; and
etching the isolation structure by using the photoresist opening to form the groove.

### Claim 17 (depends on 16)

The method for manufacturing the semiconductor structure of claim 16, further comprising: prior to the forming the first photoresist layer on the substrate,
forming a word line mask layer with a word line mask opening on the substrate; and
forming the first photoresist layer on the word line mask layer.

### Claim 18 (depends on 17)

The method for manufacturing the semiconductor structure of claim 17, wherein the word line mask opening has a first size along a direction perpendicular to an extension direction of the word line mask opening, the photoresist opening on the first photoresist layer has a second size along the direction perpendicular to the extension direction of the word line mask opening, and the second size is greater than the first size.

### Claim 19 (depends on 17)

The method for manufacturing the semiconductor structure of claim 17, wherein the formation of the first groove and the second groove at intervals on the isolation structure comprises:
etching the isolation structure by using the photoresist opening on the first photoresist layer and the word line mask layer to form the groove; and
etching the isolation structure by using the word line mask opening to form the first groove and the second groove.