# US 2022/0045069 A1 · Source/drain integration in a three-node access device for vertical three dimensional (3d) memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045069 A1 - Document ID: US20220045069A1 - Status: Published application - Kind: A1 - Application number: 16/986,510 - Filed: 2020-08-06 - Published: 2022-02-10 - Earliest claimed: 2020-08-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Scott E. Sills; John A. Smythe, III; Si-Woo Lee; Gurtej S. Sandhu; Armin Saeedi Vahdat - Web page: https://patentgrep.com/patent/US20220045069A1 ## CPC - H10B 12/05: {Making the transistor} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells} - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/485: {Bit line contacts} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region of the sacrificial material. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening. A multilayer first source/drain material, a channel material, and a second source/drain material are deposited in the first horizontal opening to form a three-node access device for a memory cell among the arrays of vertically stacked memory cells. ## Claims ### Claim 1 A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack; using a first etchant process to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent the first portion of the sacrificial material; selectively etching a first portion of the sacrificial material to form a first horizontal opening removing the sacrificial material in a first region, a first horizontal distance back from the first vertical opening to form a first and a second source/drain region separated horizontally by a channel region; and depositing a multilayer, first source/drain material, a channel material, and a second source/drain material in the first horizontal opening to form a three-node access device for a memory cell among the arrays of vertically stacked memory cells. ### Claim 2 (depends on 1) The method of claim 1, wherein depositing the multilayer first source/drain material comprises depositing a first material to form electrical contact with a storage node at a distal end of the first horizontal opening from the first vertical opening. ### Claim 3 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing a metal layer which does not oxidize in contact with an oxide semiconductor channel material in the first horizontal opening as a first material. ### Claim 4 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing a metal layer which forms a conductive oxide in contact with an oxide channel material in the first horizontal opening as a first material. ### Claim 5 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing a material containing ruthenium (Ru). ### Claim 6 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing a material containing molybdenum (Mo). ### Claim 7 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing a degenerate semiconductor material. ### Claim 8 (depends on 1) The method of claim 1, wherein depositing the multilayer, first source/drain material comprises depositing an indium tin oxide (InSnOx) material using an atomic layer deposition (ALD) process. ### Claim 9 (depends on 2) The method of claim 2, further comprising depositing a second material in electrical contact with the first material in the first horizontal opening using an atomic layer deposition (ALD) process. ### Claim 10 (depends on 9) The method of claim 9, wherein depositing the second material comprises depositing a degenerate semiconductor material. ### Claim 11 (depends on 9) The method of claim 9, wherein depositing the second material comprises depositing a second semiconductor material having an electronic bandgap lower than that of the channel material. ### Claim 12 A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack; forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack; conformally depositing first conductive material on a gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns; forming a second vertical opening exposing vertical sidewalls in the vertical stack adjacent a first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening removing the sacrificial material in a first region, a first horizontal distance back from the first vertical opening; and using a selective deposition process to deposit in the first horizontal opening: a multilayer first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening from the first vertical opening; a channel material; and a multilayer second source/drain material to form a three-node access device for a memory cell among the arrays of vertically stacked memory cells. ### Claim 13 (depends on 12) The method of claim 12, further comprising depositing an Nth source/drain material of the multilayer first source/drain material having an electronic bandgap that is intermediate between a prior (Nth-1) source/drain material and that of the channel material. ### Claim 14 (depends on 12) The method of claim 12, further comprising depositing an Nth source/drain material of the multilayer first source/drain material having a conduction band offset that is intermediate between a prior (Nth-1) source/drain material and that of the channel material. ### Claim 15 (depends on 12) The method of claim 12, further comprising depositing an Nth source/drain material of the multilayer first source/drain material, in conjunction with depositing a prior (Nth-1) source/drain material to form a compositionally graded contact material. ### Claim 16 (depends on 12) The method of claim 12, further comprising depositing a channel material having a backchannel passivation material, and in electrical contact with an Nth source/drain material. ### Claim 17 (depends on 16) The method of claim 16, wherein depositing the channel material a backchannel passivation material comprises: using an atomic layer deposition (ALD) process to form a first layer in contact with a gate dielectric of the three-node device for the memory cell; and using an ALD process to form a leakage suppression layer. ### Claim 18 (depends on 16) The method of claim 16, further comprising: depositing an indium rich, indium gallium zinc oxide (IGZO) channel material to form a first layer of the channel material in contact with a gate dielectric; and depositing an indium lean material, relative to the first layer, to form a leakage suppression layer. ### Claim 19 A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising: depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack; forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack; conformally depositing first conductive material on a gate dielectric material in the first vertical openings; removing portions of the first conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns; using a first etchant process to form a second vertical opening exposing vertical sidewalls in the vertical stack adjacent the first portion of the sacrificial material; selectively etching the first portion of the sacrificial material to form a first horizontal opening removing the sacrificial material in the first region, a first horizontal distance back from the first vertical opening; and using an atomic layer deposition (ALD) process to deposit in the first horizontal opening: a first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening from the first vertical opening; a channel material in electrical contact with the first source/drain material; and a multilayer second source/drain material in electrical contact with the channel material to form a three node access device for a memory cell among the arrays of vertically stacked memory cells. ### Claim 20 (depends on 19) The method of claim 19, wherein depositing the multilayer second source/drain material comprises depositing a first material in electrical contact with the channel material. ### Claim 21 (depends on 20) The method of claim 20, further comprising depositing a degenerative semiconductor material as the first material. ### Claim 22 (depends on 19) The method of claim 19, wherein depositing the multilayer second source/drain material comprises depositing a first semiconductor material having an electronic bandgap that is intermediate between that of the channel material and a subsequent semiconductor material formed in electrical contact with the first semiconductor material. ### Claim 23 (depends on 19) The method of claim 19, wherein depositing the multilayer second source/drain material comprises depositing a first semiconductor material having a conduction band offset that is intermediate between that of the channel material and a subsequent semiconductor material formed in electrical contact with the first semiconductor material. ### Claim 24 (depends on 19) The method of claim 19, wherein depositing the multilayer second source/drain material comprises: depositing a first semiconductor material; depositing a second semiconductor material in electrical contact with the first semiconductor material; and depositing the second semiconductor material selected based on having an electronic bandgap that is intermediate between that of the first semiconductor material and a subsequent semiconductor material formed in electrical contact with the second semiconductor material. ### Claim 25 (depends on 19) The method of claim 19, wherein depositing the multilayer second source/drain material comprises: depositing a first semiconductor material; depositing a second semiconductor material in electrical contact with the first semiconductor material; and depositing the second semiconductor material selected based on having a conduction band offset that is intermediate between that of the first semiconductor material and a subsequent semiconductor material formed in electrical contact with the second semiconductor material. ### Claim 26 (depends on 19) The method of claim 19, further comprising depositing an oxide semiconductor having a backchannel passivation material as the channel material. ### Claim 27 (depends on 19) The method of claim 19, further comprising depositing and indium gallium zinc oxide (IGZO) channel material having a backchannel passivation material as the channel material. ### Claim 28 (depends on 27) The method of claim 27, further comprising depositing the multilayer second source/drain material to have a composition which comprises one or more of an indium (In), a zinc (Zn), or a gallium (Ga) material in a varying stoichiometry to the IGZO channel material. ### Claim 29 (depends on 19) The method of claim 19, further comprising integrating a horizontally oriented digit line to form electrical contact with the multilayer second source/drain material to form the three-node access device for the memory cell without a body contact. ### Claim 30 (depends on 19) The method of claim 19, further comprising forming the vertically oriented access lines to have a horizontal width (W) which is greater than a horizontal length (L) of the channel material and overlaps both the multilayer second source/drain material and the first source/drain material horizontally. ### Claim 31 (depends on 19) The method of claim 19, further comprising forming the vertically oriented access lines to have a horizontal width (W) which is less than a horizontal length (L) of the channel material and underlaps both the multilayer second source/drain material and the first source/drain material, horizontally. ### Claim 32 A memory device, comprising: an array of vertically stacked memory cells, the array of vertically stacked memory cells, comprising: horizontally oriented, three-node access devices having a multilayer first source/drain region and a multilayer second source/drain region separated by a channel region, and gates opposing the channel region and separated therefrom by a gate dielectric, wherein the three-node access devices do not have a direct, electrical body contact to a body region or the channel region of the three-node access device; vertically oriented access lines coupled to the gates and separated from the channel region by the gate dielectric; horizontally oriented storage nodes electrically coupled to the multilayer first source/drain regions of the three-node access devices; and horizontally oriented digit lines electrically coupled to the multilayer second source/drain regions of the three-node access devices. ### Claim 33 (depends on 32) The memory device of claim 32, wherein the three-node access devices have three nodes comprising the multilayer first source/drain region (1), the multilayer second source/drain region (2), and the gates opposing the channel region (3), without having the direct, electrical body contact. ### Claim 34 (depends on 32) The memory device of claim 32, wherein the multilayer first source/drain region comprises a first material to form electrical contact with a storage node of the three-node access devices. ### Claim 35 (depends on 32) The memory device of claim 32, wherein the multilayer first source/drain region comprises a first material containing ruthenium (Ru). ### Claim 36 (depends on 32) The memory device of claim 32, wherein the multilayer first source/drain region comprises a first material containing molybdenum (Mo). ### Claim 37 (depends on 32) The memory device of claim 32, wherein the multilayer first source/drain region comprises a first material containing tin (Sn). ### Claim 38 (depends on 32) The memory device of claim 32, wherein the multilayer first source/drain region comprises a first material containing copper (Cu). ### Claim 39 (depends on 32) The memory device of claim 32, wherein the channel region comprises an oxide semiconductor material. ### Claim 40 (depends on 32) The memory device of claim 32, wherein the channel region comprises a two-dimensional (2D) material comprising one or more of a transition metal dichalcogenide. ### Claim 41 (depends on 32) The memory device of claim 32, wherein the channel region comprises a first layer having an indium rich, indium gallium zinc oxide (IGZO) channel material in contact with the gate dielectric and a gallium oxide (GaOx) leakage suppression layer as the backchannel passivation material. ### Claim 42 (depends on 32) The memory device of claim 32, wherein the horizontally oriented storage nodes comprise capacitor cells having a first horizontally oriented electrode electrically coupled to the first source/drain regions of the three-node access devices and a second horizontally oriented electrode separated from the first horizontally oriented electrode by a cell dielectric. ### Claim 43 (depends on 32) The memory device of claim 32, wherein the horizontally oriented storage nodes are in direct electrical contact with the first source/drain regions of the three-node access devices on a same plane, level with, the first source/drain regions. ### Claim 44 (depends on 32) The memory device of claim 32, wherein the horizontally oriented digit lines are in direct electrical contact with the second source/drain regions of the three-node access devices on a same plane, level with, the second source/drain regions.