# US 2022/0045068 A1 · Memory and manufacturing method thereof

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- Number: US 2022/0045068 A1
- Document ID: US20220045068A1
- Status: Published application
- Kind: A1
- Application number: 17/460,436
- Filed: 2021-08-30
- Published: 2022-02-10
- Earliest claimed: 2020-08-06
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: CHIH-CHENG LIU
- Web page: https://patentgrep.com/patent/US20220045068A1

## CPC

- H10B 99/22: {including field-effect components}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/6213: {having rounded corners}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10B 12/488: {Word lines}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

## Claims

### Claim 1

A memory, comprising:
a substrate, on which first fins and second fins are separately disposed, wherein at least two first fins are disposed between adjacent second fins, a spacing between the adjacent first fins is smaller than a spacing between the first fin and the second fin; a surface of the substrate is provided with an isolating structure comprising a first isolating structure and a second isolating structure, the first isolating structure is disposed between the adjacent first fins, and the second isolating structure is disposed between the first fin and the second fin; a dielectric layer covers tops of the first fins, side wall surfaces exposed by the isolating structure of the first fins, tops of the second fins and side wall surfaces exposed by the isolating structure of the second fins;
work function layers disposed on a surface of the dielectric layer, wherein in a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the at least two first fins are opposite are provided with a first thickness, the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness, and the first thickness is greater than the second thickness; and
a conductive layer disposed on surfaces of the work function layers.

### Claim 2 (depends on 1)

The memory of claim 1, wherein in a direction where the substrate points to the first fins, the dielectric layer and the first isolating structure are enclosed into a first filling region in an area where the adjacent first fins are opposite, and the first filling region is filled up with the work function layers.

### Claim 3 (depends on 1)

The memory of claim 1, wherein a gap is formed between the work function layers on the side walls where the at least two first fins are opposite.

### Claim 4 (depends on 1)

The memory of claim 1, wherein the work function layers comprise a first work function layer covering the whole surface of the dielectric layer and a second work function layer which is disposed on the first work function layer on the side walls where the at least two first fins are opposite.

### Claim 5 (depends on 4)

The memory of claim 4, wherein materials of the first work function layer are identical with materials of the second work function layer.

### Claim 6 (depends on 1)

The memory of claim 1, wherein the first thickness is in a range of around 5 nm to around 50 nm, and the second thickness is in a range of around 2 nm to around 30 nm.

### Claim 7 (depends on 1)

The memory of claim 1, wherein difference between the first thickness and the second thickness is in a range of around 3 nm to around 30 nm.

### Claim 8 (depends on 1)

The memory of claim 1, wherein work functions of the work function layers are greater than a work function of the conductive layer.

### Claim 9 (depends on 8)

The memory of claim 8, wherein materials of the work function layers include titanium nitride, cobalt or nickel.

### Claim 10 (depends on 2)

The memory of claim 2, wherein the first filling region is in a range of around 8 nm to around 50 nm in width.

### Claim 11

A manufacturing method of a memory, comprising:
providing a substrate, on which first fins and second fins are separately disposed, wherein at least two first fins are disposed between adjacent second fins, a spacing between the adjacent first fins is smaller than a spacing between the first fin and the second fin; a surface of the substrate is provided with an isolating structure comprising a first isolating structure and a second isolating structure, the first isolating structure is disposed between the adjacent first fins, and the second isolating structure is disposed between the first fin and the second fin;
forming a dielectric layer on tops of the first fins, side wall surfaces exposed by the isolating structure of the first fins, tops of the second fins and side wall surfaces exposed by the isolating structure of the second fins;
forming work function layers on a surface of the dielectric layer, wherein in a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the at least two first fins are opposite are provided with a first thickness, the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness, and the first thickness is greater than the second thickness; and
forming a conductive layer on surfaces of the work function layers, wherein a work function value of the conductive layer is smaller than work function values of the work function layers.

### Claim 12 (depends on 11)

The manufacturing method of the memory of claim 11, wherein in a direction where the substrate points to the first fins, the dielectric layer and the first isolating structure are enclosed into a first filling region in an area where the adjacent first fins are opposite;
wherein the forming the work function layers comprise:
forming the work function layers on the whole surface of the dielectric layer until the first filling region is filled up.

### Claim 13 (depends on 11)

The manufacturing method of the memory of claim 11, wherein the forming the work function layers comprises:
forming a first work function layer on the whole surface of the dielectric layer; and
forming a second work function layer which is disposed on the first work function layer on the side walls where the at least two first fins are opposite.

### Claim 14 (depends on 13)

The manufacturing method of the memory of claim 13, wherein the forming the second work function layer comprises:
forming a sacrificial layer on a surface of the first work function layer;
removing the sacrificial layer in an area where the adjacent first fins are opposite;
forming the second work function layer on the surface of the first work function layer in the area where the adjacent first fins are opposite; and
removing the sacrificial layer in an area where the first fin is opposite to the second fin.

### Claim 15 (depends on 11)

The manufacturing method of the memory of claim 11, further comprising:
forming a gap between the work function layers on the side walls where the at least two first fins are opposite.

### Claim 16 (depends on 13)

The manufacturing method of the memory of claim 13, wherein materials of the first work function layer are identical with materials of the second work function layer.

### Claim 17 (depends on 11)

The manufacturing method of the memory of claim 11, wherein the first thickness is in a range of around 5 nm to around 50 nm, and the second thickness is in a range of around 2 nm to around 30 nm.

### Claim 18 (depends on 11)

The manufacturing method of the memory of claim 11, wherein difference between the first thickness and the second thickness is in a range of around 3 nm to around 30 nm.

### Claim 19 (depends on 11)

The manufacturing method of the memory of claim 11, wherein work functions of the work function layers are greater than a work function of the conductive layer.

### Claim 20 (depends on 19)

The manufacturing method of the memory of claim 19, wherein materials of the work function layers include titanium nitride, cobalt or nickel.