# US 2022/0045065 A1 · Thin film transistor based memory cells on both sides of a layer of logic devices

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- Number: US 2022/0045065 A1
- Document ID: US20220045065A1
- Status: Published application
- Kind: A1
- Application number: 17/511,646
- Filed: 2021-10-27
- Published: 2022-02-10
- Earliest claimed: 2019-10-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Wilfred Gomes; Mauro J. Kobrinsky; Conor P. Puls; Kevin Fischer; Bernhard Sell; Abhishek A. Sharma; Tahir Ghani
- Web page: https://patentgrep.com/patent/US20220045065A1

## CPC

- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/05: {Making the transistor}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 1/692: {Electrodes}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 72/073: {of die-attach connectors}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

## Claims

### Claim 1

An integrated circuit (IC) device, comprising:
a first memory cell in a first layer over a support structure;
a second memory cell in a second layer over the support structure, wherein the support structure is between the first layer and the second layer; and
first-level interconnects,
wherein the second layer is between the support structure and the first-level interconnects.

### Claim 2 (depends on 1)

The IC device according to claim 1, wherein each of the first memory cell and the second memory cell includes a thin film transistor.

### Claim 3 (depends on 2)

The IC device according to claim 2, further comprising logic devices in a third layer over the support structure, wherein the third layer is between the first layer and the support structure.

### Claim 4 (depends on 1)

The IC device according to claim 1, further comprising a via extending between a first face of the support structure and a second face of the support structure, the second face being opposite the first face.

### Claim 5 (depends on 4)

The IC device according to claim 4, wherein:
the via has a first end at the first face of the support structure and a second end at the second face of the support structure,
the first end of the via is coupled to the first memory cell, and
the second end of the via is coupled to the second memory cell.

### Claim 6 (depends on 1)

The IC device according to claim 1, further comprising power and/or signal interconnects in a fourth layer over the support structure, wherein the second layer is between the support structure and the fourth layer.

### Claim 7 (depends on 1)

The IC device according to claim 1, further comprising first-level interconnects, wherein the second layer is between the support structure and the first-level interconnects.

### Claim 8 (depends on 1)

The IC device according to claim 1, further comprising a carrier substrate, wherein the first layer is between the support structure and the carrier substrate.

### Claim 9 (depends on 8)

The IC device according to claim 8, further comprising a bonding layer between the carrier substrate and the first layer.

### Claim 10

An integrated circuit (IC) device, comprising:
a first memory cell in a first layer over a support structure;
a second memory cell in a second layer over the support structure, wherein the support structure is between the first layer and the second layer;
a carrier substrate, wherein the first layer is between the support structure and the carrier substrate; and
a bonding layer between the carrier substrate and the first layer.

### Claim 11 (depends on 10)

The IC device according to claim 10, wherein each of the first memory cell and the second memory cell includes a thin film transistor.

### Claim 12 (depends on 10)

The IC device according to claim 10, further comprising logic devices in a third layer over the support structure, wherein the third layer is between the first layer and the support structure.

### Claim 13 (depends on 10)

The IC device according to claim 10, further comprising a via extending between a first face of the support structure and a second face of the support structure, the second face being opposite the first face.

### Claim 14 (depends on 13)

The IC device according to claim 13, wherein:
the via has a first end at the first face of the support structure and a second end at the second face of the support structure,
the first end of the via is coupled to the first memory cell, and
the second end of the via is coupled to the second memory cell.

### Claim 15 (depends on 10)

The IC device according to claim 10, further comprising power and/or signal interconnects in a fourth layer over the support structure, wherein the second layer is between the support structure and the fourth layer.

### Claim 16

A method of fabricating an integrated circuit (IC) device, the method comprising:
providing a first memory cell in a first layer over a support structure;
providing a second memory cell in a second layer over the support structure, wherein the support structure is between the first layer and the second layer; and
providing first-level interconnects, wherein the second layer is between the support structure and the first-level interconnects.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
providing logic devices in a third layer over the support structure, wherein the third layer is between the first layer and the support structure.

### Claim 18 (depends on 16)

The method according to claim 16, further comprising:
attaching a carrier substrate so that the first layer is between the support structure and the carrier substrate.

### Claim 19 (depends on 18)

The method according to claim 18, wherein attaching the carrier substrate include bonding the carrier substrate with a bonding material between the carrier substrate and the first layer.

### Claim 20 (depends on 16)

The method according to claim 16, wherein each of the first memory cell and the second memory cell includes a thin film transistor.