# US 2022/0045054 A9 · Cmos structure and method for manufacturing cmos structure

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- Number: US 2022/0045054 A9
- Document ID: US20220045054A9
- Status: Published application
- Kind: A9
- Application number: 16/642,723
- Filed: 2019-03-04
- Published: 2022-02-10
- Earliest claimed: 2019-03-04
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Zhi WANG; Feng GUAN; Guangcai YUAN; Chen XU; Lei CHEN
- Web page: https://patentgrep.com/patent/US20220045054A9

## CPC

- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

## Claims

### Claim 1

A CMOS structure comprising a substrate and an N-type TFT and a P-type TFT on the substrate, wherein the N-type TFT comprises:
a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer, wherein the first active layer comprises a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer, wherein an N-type doping concentration of the second semiconductor layer is smaller than an N-type doping concentration of the third semiconductor layer, and wherein the P-type TFT comprises:
a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the second active layer comprises a fourth semiconductor layer, and a fifth semiconductor layer of the P-type and a sixth semiconductor layer of the P type which are at the opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer, and wherein a P-type doping concentration of the fifth semiconductor layer is smaller than a P-type doping concentration of the sixth semiconductor layer.

### Claim 2 (depends on 1)

The CMOS structure according to claim 1, wherein at least a portion of the first semiconductor layer serving as a channel region and a portion of the fourth semiconductor layer serving as a channel region comprise a polycrystalline semiconductor material.

### Claim 3 (depends on 2)

The CMOS structure according to claim 2, wherein source/drain regions of the first semiconductor layer and source/drain regions of the fourth semiconductor layer include an amorphous semiconductor material.

### Claim 4 (depends on 3)

The CMOS structure according to claim 3, wherein the second semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer comprise the polycrystalline semiconductor material.

### Claim 5 (depends on 4)

The CMOS structure according to claim 4, wherein
the polycrystalline semiconductor material comprises polysilicon, and wherein the amorphous semiconductor material comprises amorphous silicon.

### Claim 6 (depends on 3)

The CMOS structure according to claim 3, wherein
the N-type TFT further comprises a first etch stop layer on a side, away from the first gate dielectric layer, of a portion of the first semiconductor layer serving as a channel region portion, an end portion of the first etch stop layer located between the first semiconductor layer and the second semiconductor layer, and wherein the P-type TFT further comprises a second etch stop layer on a side, away from the second gate dielectric layer, of a portion of the fourth semiconductor layer serving as a channel region, an end of the second etch stop layer located between the fourth semiconductor layer and the fifth semiconductor layer.

### Claim 7 (depends on 1)

The CMOS structure according to claim 1, wherein the first gate electrode, the first gate dielectric layer, and the first semiconductor layer are sequentially stacked in a direction away from the substrate, and wherein the second gate electrode, the second gate dielectric layer, and the second semiconductor layer are sequentially stacked in a direction away from the substrate.

### Claim 8 (depends on 7)

The CMOS structure according to claim 7, wherein the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region away from the P-type TFT, wherein the second active layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region away from the P-type TFT, and wherein the CMOS structure further comprises:
a first source/drain electrode disposed on the first source/drain region;
a second source/drain electrode disposed on the second source/drain region;
a third source/drain electrode disposed on the third source/drain region; and
a fourth source/drain electrode disposed on the fourth source/drain region, wherein the first source/drain electrode is connected to the third source/drain electrode.

### Claim 9

A method for manufacturing a CMOS structure, comprising forming an N-type TFT and a P-type TFT on a substrate, wherein forming the N-type TFT comprises:
forming a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer, wherein the first active layer comprises a first semiconductor layer, a second semiconductor layer of the N-Type, and an third semiconductor layer of the N-type which are at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer, wherein an N-type doping concentration of the second semiconductor layer is smaller than an N-type doping concentration of the third semiconductor layer, and wherein forming the P-type TFT comprises:
forming a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the second active layer comprises a fourth semiconductor layer, a fifth semiconductor layer of the P-type, and a sixth semiconductor layer of the P-type which are at opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer, and wherein a P-type doping concentration of the fifth semiconductor layer is smaller than a P-type doping concentration of the sixth semiconductor layer.

### Claim 10 (depends on 9)

The method for manufacturing a CMOS structure according to claim 9, wherein at least a channel region of the first semiconductor layer and a channel region of the fourth semiconductor layer comprise a polycrystalline semiconductor material, and wherein source/drain regions of the first semiconductor layer and source/drain regions of the fourth semiconductor layer comprise an amorphous semiconductor material.

### Claim 11 (depends on 10)

The method for manufacturing a CMOS structure according to claim 10, wherein forming the first gate dielectric layer and the second gate dielectric layer comprises forming a gate dielectric material layer on the first gate electrode and the second gate electrode, wherein a portion of the gate material dielectric layer on the first gate electrode constitutes the first gate dielectric layer, and wherein a portion of the gate material dielectric layer on the second gate electrode constitutes the second gate dielectric layer.

### Claim 12 (depends on 11)

The method for manufacturing a CMOS structure according to claim 11, wherein forming the first semiconductor layer and the second semiconductor layer comprises:
forming a first amorphous semiconductor material on the gate dielectric material layer; and
converting portions of the first amorphous semiconductor material layer on the first gate electrode and the second gate electrode into a polycrystalline semiconductor material to form a channel region of the first active layer and a channel region of the second active layer.

### Claim 13 (depends on 12)

The method for manufacturing a CMOS structure according to claim 12, wherein the converting comprises performing laser annealing on the amorphous semiconductor material.

### Claim 14 (depends on 13)

The method for manufacturing a CMOS structure according to claim 13, wherein the laser annealing comprises using a microlens array mask.

### Claim 15 (depends on 9)

The method for manufacturing a CMOS structure according to claim 9, further comprising:
forming a first etch stop layer on a portion of the first semiconductor layer serving as a channel region; and
forming a second etch stop layer on a portion of the fourth semiconductor layer serving as a channel region.

### Claim 16 (depends on 15)

The method for manufacturing a CMOS structure according to claim 15, wherein forming the second semiconductor layer and the third semiconductor layer comprises:
forming a second amorphous semiconductor material layer on the first semiconductor layer;
forming a third amorphous semiconductor material layer on the second amorphous semiconductor material layer; and
etching the second amorphous semiconductor material layer and the third amorphous semiconductor material layer located on the first etch stop layer to form a first gap extending to the first etch stop layer.

### Claim 17 (depends on 15)

The method for manufacturing a CMOS structure according to claim 15, wherein forming the fifth semiconductor layer and the sixth semiconductor layer comprises:
forming a fifth amorphous semiconductor material layer on the fourth semiconductor layer;
forming a sixth amorphous semiconductor material layer on the fifth amorphous semiconductor material layer; and
etching the fifth amorphous semiconductor material layer and the sixth amorphous semiconductor material layer located on the second etch stop layer to form a second gap extending to the second etch stop layer.

### Claim 18 (depends on 16)

The method for manufacturing a CMOS structure according to claim 16, wherein forming the second amorphous semiconductor material layer, the third amorphous semiconductor material layer, the fifth amorphous semiconductor material layer, and the sixth amorphous semiconductor material layer comprises using CVD.

### Claim 19 (depends on 16)

The method for manufacturing a CMOS structure according to claim 16, wherein the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region away from the P-type TFT, and wherein the second active layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region away from the N-type TFT, the method further comprising:
forming a conductive layer on the third semiconductor layer, the sixth semiconductor layer, the first gate dielectric layer, and the second gate dielectric layer; and
etching the conductive layer to form a first portion, a second portion, and a third portion spaced from one another, wherein the first portion covers the first source/drain region and the third source/drain region, wherein, the second portion covers the second source/drain region, and wherein the third portion covers the fourth source/drain region.

### Claim 20 (depends on 18)

The method for manufacturing a CMOS structure according to claim 18, wherein the polycrystalline semiconductor material comprises polysilicon, and wherein the amorphous semiconductor material comprises amorphous silicon.