# US 2022/0045052 A1 · Backside pn junction diode

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- Number: US 2022/0045052 A1
- Document ID: US20220045052A1
- Status: Published application
- Kind: A1
- Application number: 17/510,014
- Filed: 2021-10-25
- Published: 2022-02-10
- Earliest claimed: 2020-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Xuan Huang; Ching-Wei Tsai; Jam-Wem Lee; Kuo-Ji Chen; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US20220045052A1

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/221: {of only diodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a well region surrounded by an isolation feature and extending lengthwise along a first direction,
a source feature and a drain feature over the well region;
a plurality of nanostructures extending between the source feature and the drain feature along the first direction;
a gate structure wrapping around each of the plurality of nanostructures;
an epitaxial layer disposed below and in contact with the well region;
a silicide layer disposed below and in contact with the epitaxial layer; and
a backside conductive feature disposed below and in contact with the silicide layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1,
wherein the well region and the epitaxial layer are doped with the same type of dopant,
wherein a doping concentration of the epitaxial layer is greater than a doping concentration of the well region.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the silicide layer comprises titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN).

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the gate structure is electrically floating.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the source feature and the drain feature are doped with the same type of dopant.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the source feature is resistively coupled to the drain feature.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the source feature and the drain feature are doped with the different types of dopants.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the source feature is resistively coupled to the backside conductive feature.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the gate structure is spaced apart from the source feature and the drain feature by a plurality of inner spacer features.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a source contact disposed over and in contact with the source feature; and
a drain contact disposed over and in contact with the drain feature.

### Claim 11

A semiconductor structure, comprising:
a well region surrounded by an isolation feature and extending along a first direction,
a source feature and a drain feature over the well region;
a source contact disposed over and in contact with the source feature and a drain contact disposed over and in contact with the drain feature;
a plurality of channel members extending between the source feature and the drain feature along the first direction;
a gate structure wrapping around each of the plurality of channel members;
an epitaxial layer disposed below and in contact with the well region;
a silicide layer disposed below and in contact with the epitaxial layer; and
a backside conductive feature disposed below and in contact with the silicide layer,
wherein the gate structure is electrically floating.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the well region and the epitaxial layer comprise a total thickness between about 30 nm and about 150 nm.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, wherein the silicide layer comprises a thickness between about 3 nm and about 5 nm.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11, wherein the backside conductive feature comprises tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu).

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein the silicide layer comprises titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN).

### Claim 16

A device, comprising:
a first PN junction diode comprising:
a well region doped with a dopant of a first conductivity type,
a first epitaxial feature disposed over the well region, the first epitaxial feature being doped with a dopant of a second conductivity type different from the first conductivity type,
a first contact disposed on and in contact with the first epitaxial feature, and
a backside conductive feature disposed below the well region; and
a second PN junction diode comprising:
the well region,
a second epitaxial feature disposed over the well region and spaced apart from the first epitaxial feature, the second epitaxial feature being doped with the dopant of the second conductivity type, and
a second contact disposed on and in contact with the second epitaxial feature.

### Claim 17 (depends on 16)

The device of claim 16, further comprising:
a plurality of nanostructures extending between the first epitaxial feature and the second epitaxial feature; and
a metal structure wrapping around each of the plurality of nano structures.

### Claim 18 (depends on 17)

The device of claim 17, wherein the metal structure is electrically floating.

### Claim 19 (depends on 16)

The device of claim 16, further comprising:
a backside epitaxial layer disposed between the well region and the backside conductive feature; and
a silicide layer disposed between the backside epitaxial layer and the backside conductive feature.

### Claim 20 (depends on 16)

The device of claim 16, wherein the first epitaxial feature is resistively coupled to the second epitaxial feature.