# US 2022/0045049 A1 · Device including mim capacitor and resistor

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- Number: US 2022/0045049 A1
- Document ID: US20220045049A1
- Status: Published application
- Kind: A1
- Application number: 17/508,470
- Filed: 2021-10-22
- Published: 2022-02-10
- Earliest claimed: 2018-04-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hsiang HUNG; Li-Hsin CHU; Chia-Ping LAI; Chung-Chuan TSENT
- Web page: https://patentgrep.com/patent/US20220045049A1

## CPC

- H10D 84/206: {of combinations of capacitors and resistors}
- H10D 1/47: Resistors having no potential barriers
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 1/692: {Electrodes}
- H10D 86/85: characterised by only passive components
- H10W 20/48: Insulating materials thereof
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

## Claims

### Claim 1

A method, comprising:
providing a first dielectric layer;
sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and
using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
recessing the dummy capacitor dielectric layer and the first metal layer so as to define a capacitor dielectric layer and a bottom metal plate of the capacitor.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming at least a first contact and a second contact, extending through a second dielectric layer, to couple the bottom and top metal plates of the capacitor, respectively; and
forming at least a third contact and a fourth contact, extending through the second dielectric layer, to couple the metal thin film of the resistor,
wherein the second dielectric layer is formed above the first dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a first etch stop layer below the bottom metal plate; and
forming a second etch top layer disposed on a portion of the top surface of the top metal plate and on a portion of a top surface of the metal thin film, wherein the first and the second etch stop layers are each configured to buffer a respective etching process, wherein the second etch stop layer comprises a first portion disposed on the top surface of the metal thin film and a second portion disposed on the top surface of the top metal plate, wherein the first portion, metal thin film, the second portion and the top metal plate are formed using a single first etching mask, and wherein the patterned dielectric layer, the capacitor dielectric layer, the patterned metal layer and bottom metal plate are formed using a single second etching mask.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a first dielectric layer over the capacitor and the resistor, the first dielectric layer having a portion that extends between the capacitor and the resistor into the first etch stop layer;
forming a second dielectric layer below the first dielectric layer; and
forming a sealing layer disposed between the first etch stop layer and the second dielectric layer, wherein the sealing layer comprises silicon nitride.

### Claim 6

A method of making a semiconductor device, comprising:
forming a bottom metal plate over a substrate;
forming a capacitor dielectric layer over the bottom metal plate;
forming a top metal plate over the capacitor dielectric layer, wherein the capacitor dielectric layer includes a planar lower surface directly contacting a planar top surface of the bottom metal plate and wherein the capacitor dielectric layer includes a planar upper surface directly contacting a planar bottom surface of the top metal plate; and
simultaneously forming a metal thin film with the top metal plate, wherein the metal thin film of the resistor and the top metal plate of the capacitor are formed of a same metal material, and wherein a top surface of the metal thin film is substantially coplanar with a top surface of the top metal plate of the capacitor, wherein the metal thin film is formed over a patterned dielectric layer, the patterned dielectric layer being formed of a same material as the capacitor dielectric layer, and wherein the patterned dielectric layer is formed over a patterned metal layer, the patterned metal layer being simultaneously formed of a same material as the bottom metal plate.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
forming a first etch stop layer below the patterned metal layer and the bottom metal plate, wherein the first etch stop layer presents a different etch selectivity as compared to the etch selectivity of the capacitor dielectric layer; and
forming a second etch top layer disposed on a portion of the top surface of the top metal plate and on a portion of a top surface of the metal thin film, wherein the first and the second etch stop layers are each configured to buffer a respective etching process, wherein the second etch stop layer comprises a first portion disposed on the top surface of the metal thin film and a second portion disposed on the top surface of the top metal plate, wherein the first portion, metal thin film, the second portion and the top metal plate are formed using a single first etching mask, and wherein the patterned dielectric layer, the capacitor dielectric layer, the patterned metal layer and bottom metal plate are formed using a single second etching mask.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming a first dielectric layer over the capacitor and the resistor, the first dielectric layer having a portion that extends between the capacitor and the resistor into the first etch stop layer;
forming a second dielectric layer below the first dielectric layer; and
forming a sealing layer between the first etch stop layer and the second dielectric layer, wherein the sealing layer comprises silicon nitride.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first and second dielectric layers are each formed of a low-k dielectric material.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
forming a first contact, extending through the first dielectric layer, coupled to a portion of the planar top surface of the bottom metal plate of the capacitor; and
forming a second contact, extending through the first dielectric layer, coupled to a portion of a planar top surface of the top metal plate of the capacitor.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a third contact, extending through the first dielectric layer, coupled to a first portion of the top surface of the metal thin film of the resistor; and
forming a fourth contact, extending through the first dielectric layer, coupled to a second portion of the top surface of the metal thin film of the resistor.

### Claim 12 (depends on 7)

The method of claim 7, wherein the first and second portions are located on both ends of the metal thin film of the resistor, respectively.

### Claim 13

A method of making a semiconductor device, comprising:
forming a capacitor comprising: a bottom metal plate, a capacitor dielectric layer, and a top metal plate, wherein the capacitor dielectric layer is sandwiched between the bottom and top metal plates, wherein the capacitor dielectric layer includes a planar lower surface directly contacting a planar top surface of the bottom metal plate and wherein the capacitor dielectric layer includes a planar upper surface directly contacting a planar bottom surface of the top metal plate;
forming a resistor comprising a metal thin film, wherein the metal thin film of the resistor and the top metal plate of the capacitor are simultaneously formed from a same patterning process, wherein the metal thin film is formed over a patterned dielectric layer, the patterned dielectric layer being formed of a same material as the capacitor dielectric layer, and wherein the patterned dielectric layer is formed over a patterned metal layer, the patterned metal layer being formed of a same material as the bottom metal plate;
forming a first etch stop layer below the patterned metal layer and the bottom metal plate, wherein the first etch stop layer presents a different etch selectivity as compared to the etch selectivity of the capacitor dielectric layer; and
forming a second etch top layer on a portion of a top surface of the top metal plate and on a portion of a top surface of the metal thin film, wherein the first and the second etch stop layers are each configured to buffer a respective etching process, wherein the second etch stop layer comprises a first portion disposed on the top surface of the metal thin film and a second portion disposed on the top surface of the top metal plate, wherein the first portion, metal thin film, the second portion and the top metal plate are formed using a single first etching mask, and wherein the patterned dielectric layer, the capacitor dielectric layer, the patterned metal layer and bottom metal plate are formed using a single second etching mask.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a first dielectric layer over the capacitor and the resistor, the first dielectric layer having a portion that extends between the capacitor and the resistor into the first etch stop layer;
forming a second dielectric layer below the first dielectric layer; and
forming a sealing layer between the first etch stop layer and the second dielectric layer, wherein the sealing layer comprises silicon nitride.

### Claim 15 (depends on 13)

The method of claim 13, wherein the metal thin film of the resistor and the top metal plate of the capacitor are formed of a same metal material.

### Claim 16 (depends on 15)

The method of claim 15, wherein the same metal material is selected from at least one of:
Ta, TaN, Ti, TiN, W, WN, NiCr, SiCr, and a combination thereof.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first and second dielectric layers are each formed of a low-k dielectric material.

### Claim 18 (depends on 13)

The method of claim 13, further comprising:
forming a first contact, extending through the first dielectric layer, coupled to a portion of the planar top surface of the top metal plate of the capacitor; and
forming a second contact, extending through the first dielectric layer, coupled to a portion of a planar top surface of the bottom metal plate of the capacitor.

### Claim 19 (depends on 13)

The method of claim 13, further comprising:
forming a third contact, extending through the first dielectric layer, coupled to a first portion of a top surface of the metal thin film of the resistor; and
forming a fourth contact, extending through the first dielectric layer, coupled to a second portion of the top surface of the metal thin film of the resistor.

### Claim 20 (depends on 13)

The method of claim 13, wherein the capacitor dielectric layer is formed of a material selected from at least one of: Al2O3, HfO2, SiO2, La2O3, ZrO3, Ba—Sr—Ti—O, Si3N4, and a combination thereof.