# US 2022/0045048 A1 · Semiconductor apparatus

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- Number: US 2022/0045048 A1
- Document ID: US20220045048A1
- Status: Published application
- Kind: A1
- Application number: 17/505,793
- Filed: 2021-10-20
- Published: 2022-02-10
- Earliest claimed: 2018-11-26
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Tetsuo TAKAHASHI
- Web page: https://patentgrep.com/patent/US20220045048A1

## CPC

- H10D 84/617: {Combinations of vertical BJTs and only diodes}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 8/422: {PN diodes having the PN junctions in mesas}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n− drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

## Claims

### Claim 1

A semiconductor apparatus comprising:
a semiconductor substrate having a front surface and a back surface;
a first electrode provided on the front surface; and
a second electrode provided on the back surface,
the semiconductor substrate including a device region including a first semiconductor device, and a peripheral region surrounding the device region,
the first semiconductor device including an n− drift region, a p base region, an n+ emitter region being in contact with the first electrode, a gate insulating film provided on a portion of the p base region between the n+ emitter region and the n− drift region, a gate electrode facing the portion of the p base region with the gate insulating film interposed therebetween, an n buffer layer being in contact with the n− drift region and provided on the back surface side with respect to the n− drift region, and a p collector layer being in contact with the n buffer layer and provided on the back surface side with respect to the n buffer layer,
the n− drift region, the n buffer layer, the p collector layer and the second electrode extending from the device region to the peripheral region, and
the peripheral region being provided with an n type region, the n type region being in contact with the second electrode, and the p collector layer including a p collector portion between the n buffer layer and the n type region.

### Claim 2 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
the n type region extends at least from a peripheral end of the device region to a first portion of the peripheral region, the first portion is spaced apart from the peripheral end by a thickness of the semiconductor substrate, and the thickness of the semiconductor substrate is defined as a distance between the front surface and the back surface at the peripheral end.

### Claim 3 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
in a plan view of the back surface, the n type region includes a plurality of n type region portions, and
the plurality of n type region portions are arranged discretely in the peripheral region.

### Claim 4 (depends on 1)

The semiconductor apparatus according to claim 1, wherein
the device region further includes a second semiconductor device, and
the second semiconductor device includes a p anode layer provided on the front surface side with respect to the n− drift region, and an n+ cathode layer provided on the back surface side with respect to the n− drift region.

### Claim 5

A semiconductor apparatus comprising:
a semiconductor substrate having a front surface and a back surface;
a first electrode provided on the front surface; and
a second electrode provided on the back surface,
the semiconductor substrate including a device region including a first semiconductor device, and a peripheral region surrounding the device region,
the first semiconductor device including an n− drift region, a p base region, an n+ emitter region being in contact with the first electrode, a gate insulating film provided on a portion of the p base region between the n+ emitter region and the n− drift region, a gate electrode facing the portion of the p base region with the gate insulating film interposed therebetween, and a p collector layer provided on the back surface side with respect to the n− drift region and being in contact with the second electrode,
the n− drift region and the second electrode extending from the device region to the peripheral region, and
the peripheral region being provided with an insulating region, the insulating region being between the n− drift region and the second electrode, and being in contact with the second electrode.

### Claim 6 (depends on 5)

The semiconductor apparatus according to claim 5, wherein
the insulating region extends at least from a peripheral end of the device region to a first portion of the peripheral region, the first portion is spaced apart from the peripheral end by a thickness of the semiconductor substrate, and the thickness of the semiconductor substrate is defined as a distance between the front surface and the back surface at the peripheral end.

### Claim 7 (depends on 5)

The semiconductor apparatus according to claim 5, wherein
in a plan view of the back surface, the insulating region includes a plurality of insulating region portions, and
the plurality of insulating region portions are arranged discretely in the peripheral region.

### Claim 8 (depends on 5)

The semiconductor apparatus according to claim 5, wherein
the device region further includes a second semiconductor device, and
the second semiconductor device includes a p anode layer provided on the front surface side with respect to the n− drift region, and an n+ cathode layer provided on the back surface side with respect to the n− drift region.