# US 2022/0045045 A1 · Semiconductor memory device and manufacturing method of semiconductor memory device

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- Number: US 2022/0045045 A1
- Document ID: US20220045045A1
- Status: Published application
- Kind: A1
- Application number: 17/165,408
- Filed: 2021-02-02
- Published: 2022-02-10
- Earliest claimed: 2020-08-06
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Nam Jae LEE
- Web page: https://patentgrep.com/patent/US20220045045A1

## CPC

- H10W 90/00: Package configurations
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/07331: {Connecting techniques}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.

## Claims

### Claim 1

A semiconductor memory device comprising:
a peripheral circuit layer;
a bonding structure disposed on the peripheral circuit layer;
a channel structure disposed on the bonding structure;
a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and
a first gate conductive pattern in contact with a sidewall of the first horizontal part and spaced apart from the first vertical part, wherein the first gate conductive pattern extends to surround the channel structure.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the bonding structure includes a structure in which dielectric layers are bonded together.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a second gate conductive pattern surrounding the channel structure, the second gate conductive pattern disposed between the first gate conductive pattern and the bonding structure; and
a second gate contact structure disposed between the second gate conductive pattern and the first gate contact structure,
wherein the second gate contact structure includes a second vertical part penetrating the bonding structure and the first gate conductive pattern and a second horizontal part extending from the second vertical part, and
wherein a sidewall of the second horizontal part is in contact with the second gate conductive pattern.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein the first gate conductive pattern further protrudes toward the first gate contact structure than the second gate conductive pattern.

### Claim 5

The semiconductor memory device of claim further comprising:
a first interlayer insulating layer surrounding the channel structure between the first gate conductive pattern and the second gate conductive pattern;
a second interlayer insulating layer overlapping with the first interlayer insulating layer with the first gate conductive pattern interposed between the second interlayer insulating layer and the first interlayer insulating layer, wherein the second interlayer insulating layer surrounds the channel structure;
a first gate spacer insulating layer surrounding a sidewall of the first vertical part, wherein the first gate spacer insulating layer is penetrated by the first horizontal part; and
a second gate spacer insulating layer surrounding a sidewall of the second vertical part, wherein the second gate spacer insulating layer is penetrated by the second horizontal part.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5, wherein each of the first gate spacer insulating layer and the second gate spacer insulating layer protrudes toward the first gate conductive pattern to fill a gap between the first interlayer insulating layer and the second interlayer insulating layer.

### Claim 7 (depends on 5)

The semiconductor memory device of claim 5, wherein each of the first gate spacer insulating layer and the second gate spacer insulating layer includes a bottom surface which faces the peripheral circuit layer and overlaps with the bonding structure.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein the peripheral circuit layer includes:
a substrate including an impurity region;
an interconnection structure connected to the impurity region; and
a conductive pad connected to the interconnection structure and overlapping with the first vertical part.

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein the first vertical part extends to be in contact with the conductive pad.

### Claim 10

A semiconductor memory device comprising:
a peripheral circuit layer including a first region and a second region;
a bonding structure disposed on the peripheral circuit layer;
a cell stack structure overlapping with the first region, the cell stack structure including gate conductive patterns and interlayer insulating layers, which are alternately stacked on the bonding structure;
a channel structure penetrating the cell stack structure;
a dummy stack structure overlapping with the second region, wherein the dummy stack structure includes first material layers and second material layers, which are alternately stacked on the bonding structure;
a vertical contact structure penetrating the dummy stack structure and the bonding structure to be connected to the peripheral circuit layer; and
a dummy spacer insulating layer surrounding a sidewall of the vertical contact structure,
wherein the dummy spacer insulating layer includes a pillar part extending along the sidewall of the vertical contact structure and protrusion parts protruding toward the second material layers from the pillar part to fill spaces between the first material layers.

### Claim 11 (depends on 10)

The semiconductor memory device of claim 10, wherein the pillar part includes a bottom surface which faces the peripheral circuit layer and overlaps with the bonding structure.

### Claim 12 (depends on 10)

The semiconductor memory device of claim 10, wherein the bonding structure includes a structure in which dielectric layers are bonded together.

### Claim 13 (depends on 10)

The semiconductor memory device of claim 10, wherein the gate conductive patterns include:
a first gate conductive pattern disposed on the bonding structure; and
a second gate conductive pattern disposed between the first gate conductive pattern and the bonding structure, and
wherein the first gate conductive pattern extends more distant from the channel structure than the second gate conductive pattern.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, further comprising:
a first gate contact structure including a first vertical part extending substantially in parallel to the channel structure and a horizontal part extending from the first vertical part at a level at which the first gate conductive pattern is disposed to be in contact with the first gate conductive pattern; and
a second gate contact structure including a second vertical part extending substantially in parallel to the channel structure and a second horizontal part extending from the second vertical part at a level at which the second gate conductive pattern is disposed to be in contact with the second gate conductive pattern.

### Claim 15 (depends on 14)

The semiconductor memory device of claim 14, further comprising:
a first gate spacer insulating layer surrounding a sidewall of the first vertical part, wherein the first gate spacer insulating layer is penetrated by the first horizontal part; and
a second gate spacer insulating layer surrounding a sidewall of the second vertical part, wherein the second gate spacer insulating layer is penetrated by the second horizontal part.

### Claim 16 (depends on 15)

The semiconductor memory device of claim 15, wherein the first gate spacer insulating layer is formed in an asymmetrical structure with respect to the first horizontal part, and
the second gate spacer insulating layer is formed in an asymmetrical structure with respect to the second horizontal part.

### Claim 17 (depends on 15)

The semiconductor memory device of claim 15, wherein the first gate spacer insulating layer protrudes toward the first gate conductive pattern, and
the second gate spacer insulating layer protrudes toward the first gate conductive pattern and the second gate conductive pattern.

### Claim 18 (depends on 14)

The semiconductor memory device of claim 14, wherein the peripheral circuit layer includes:
a plurality of transistors isolated from each other by an isolation layer;
interconnection structures connected to the transistors; and
conductive pads connected to the interconnection structures.

### Claim 19 (depends on 18)

The semiconductor memory device of claim 18, wherein the conductive pads respectively overlap with the first vertical part, the second vertical part, and the vertical contact structure, and
wherein the first vertical part, the second vertical part, and the vertical contact structure extend to be respectively in contact with the conductive pads.