# US 2022/0045038 A1 · Semiconductor package

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- Number: US 2022/0045038 A1
- Document ID: US20220045038A1
- Status: Published application
- Kind: A1
- Application number: 17/389,561
- Filed: 2021-07-30
- Published: 2022-02-10
- Earliest claimed: 2020-08-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hee Woo AN; Kyung Suk OH; Man ho LEE
- Web page: https://patentgrep.com/patent/US20220045038A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package including a first package including a memory chip having a memory cell, and a capacitor structure disposed independently of the memory chip; and a second package including a logic chip configured to access the memory cell, wherein the capacitor structure is electrically connected to the memory chip and the logic chip.

## Claims

### Claim 1

A semiconductor package, comprising:
a first package including:
a memory chip having a memory cell, and
a capacitor structure disposed independently of the memory chip; and
a second package including a logic chip configured to access the memory cell,
wherein the capacitor structure is electrically connected to the memory chip and the logic chip.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, wherein:
the first package further includes:
a first interconnection structure including at least one first interconnection layer, the memory chip and the capacitor structure being separate from each other and on a first surface of the first interconnection structure; and
a first molding part covering a first surface of the memory chip and a first surface of the capacitor structure, and the second package is on a second surface of the first interconnection structure,
the second surface of the first interconnection structure being opposite to the first surface of the first interconnection structure.

### Claim 3 (depends on 2)

The semiconductor package as claimed in claim 2, wherein the second package further includes:
a second interconnection structure including at least one second interconnection layer, the logic chip being on a first surface of the second interconnection structure;
at least one via electrically connecting the first interconnection structure and the second interconnection structure; and
a second molding part between the first interconnection structure and the second interconnection structure.

### Claim 4 (depends on 3)

The semiconductor package as claimed in claim 3, wherein the second package includes a plurality of solder balls on a second surface of the second interconnection structure, the second surface of the second interconnection structure being opposite to the first surface of the second interconnection structure.

### Claim 5 (depends on 3)

The semiconductor package as claimed in claim 3, wherein the memory chip and the capacitor structure are electrically connected to the logic chip through the at least one first interconnection layer of the first interconnection structure and the at least one via connected to the at least one first interconnection layer.

### Claim 6 (depends on 3)

The semiconductor package as claimed in claim 3, wherein the first package further includes:
an integrated stack capacitor (ISC) covering both of an upper surface of the memory chip and an upper surface of the capacitor structure; and
a wire connected to the at least one first interconnection layer in the first interconnection structure and connected to the ISC.

### Claim 7 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising a substrate,
wherein the first package and the second package are side-by-side on a first surface of the substrate.

### Claim 8 (depends on 7)

The semiconductor package as claimed in claim 7, wherein:
the substrate includes a third interconnection layer on the first surface thereof and a third insulating layer stacked on the third interconnection layer, and
the third interconnection layer is electrically connected to the first package and the second package.

### Claim 9 (depends on 7)

The semiconductor package as claimed in claim 7, wherein:
the first package further includes an integrated stack capacitor between a lower surface of the memory chip and the substrate, and
the second package is electrically connected to the integrated stack capacitor and the capacitor structure.

### Claim 10

A semiconductor package, comprising:
an integrated stack capacitor (ISC) including a first surface and a second surface opposite to the first surface;
a memory chip having one surface on the first surface of the ISC and including a plurality of memory cells; and
a logic chip having one surface on the second surface of the ISC and being configured to access the memory cell,
wherein the ISC is electrically connected to the memory chip and electrically connected to the logic chip.

### Claim 11 (depends on 10)

The semiconductor package as claimed in claim 10, wherein:
the semiconductor package includes a first package and a second package,
the first package includes:
the memory chip;
the ISC;
a first interconnection structure having one surface on the second surface of the ISC; and
a plurality of solder balls on another surface of the first
interconnection structure, and
the second package includes the logic chip electrically connected to the plurality of solder balls.

### Claim 12 (depends on 10)

The semiconductor package as claimed in claim 10, further comprising:
a substrate on another surface of the logic chip; and
a molding part surrounding the memory chip, the ISC, and the logic chip.

### Claim 13

A semiconductor package, comprising:
a memory chip including a memory cell;
a logic chip configured to access the memory cell; and
an integrated stack capacitor (ISC) electrically connected to the memory chip and electrically connected to the logic chip.

### Claim 14 (depends on 13)

The semiconductor package as claimed in claim 13, wherein:
the semiconductor package includes a first package and a second package on a lower surface of the first package, the first package includes:
the ISC;
a first interconnection structure including at least one first interconnection layer;
the memory chip between a portion of an upper surface of the first interconnection structure and a lower surface of the ISC;
a capacitor structure between remaining portions of the upper surface of the first interconnection structure and the lower surface of the ISC; and
at least one wire electrically connecting the first interconnection layer and the ISC, and
the second package includes the logic chip and is electrically connected to the ISC.

### Claim 15 (depends on 14)

The semiconductor package as claimed in claim 14, wherein the second package further includes:
a second interconnection structure including at least one second interconnection layer, the logic chip being on an upper surface of the second interconnection structure;
at least one via electrically connecting the first interconnection layer and the second interconnection layer; and
a second molding part between the first interconnection structure and the second interconnection structure.

### Claim 16 (depends on 13)

The semiconductor package as claimed in claim 13, wherein:
the semiconductor package includes a substrate, and a first package and a second package which are separated from each other on a first surface of the substrate,
the first package includes:
a first interconnection structure including at least one first interconnection layer;
the memory chip on one portion of an upper surface of the first interconnection structure;
a capacitor structure on remaining portions of the upper surface of the first interconnection structure;
the ISC having one surface on a lower surface of the first interconnection structure;
first solder balls between another surface of the ISC and the first surface of the substrate; and
a first molding part surrounding the memory chip, the capacitor structure, and the ISC, and
the second package includes the logic chip sharing the ISC and the capacitor structure.

### Claim 17 (depends on 16)

The semiconductor package as claimed in claim 16, wherein the second package further includes:
a second interconnection structure including at least one second interconnection layer, the logic chip being on an upper surface of the second package;
at least one second solder ball on a lower surface of the second interconnection structure; and
a second molding part surrounding the logic chip.

### Claim 18 (depends on 16)

The semiconductor package as claimed in claim 16, wherein the substrate includes:
a third insulating layer between the first package and the second package and the first surface; and
a third interconnection layer under the third insulating layer and electrically connected to the first package and the second package.

### Claim 19 (depends on 13)

The semiconductor package as claimed in claim 13, wherein:
the memory chip is on a first surface of the ISC, and
the logic chip is on a second surface of the ISC, the second surface being opposite to the first surface of the ISC.

### Claim 20 (depends on 19)

The semiconductor package as claimed in claim 19, further comprising a through-via passing through the ISC and directly electrically connecting the memory chip and the logic chip.