# US 2022/0045037 A1 · Semiconductor device and method of manufacturing a semiconductor device

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- Number: US 2022/0045037 A1
- Document ID: US20220045037A1
- Status: Published application
- Kind: A1
- Application number: 17/510,598
- Filed: 2021-10-26
- Published: 2022-02-10
- Earliest claimed: 2019-05-28
- Assignees: Amkor Technology Singapore Holding Pte. Ltd.
- Applicants: Amkor Technology Singapore Holding Pte. Ltd.
- Inventors: In Su Mok; Won Geol Lee; Il Bok Lee; Won Myoung Ki
- Web page: https://patentgrep.com/patent/US20220045037A1

## CPC

- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one example, a semiconductor device comprises a base assembly comprising a first substrate, a first device on a top surface of the first substrate, and a first encapsulant on the top surface of the first substrate and bounding a side surface of the first device. The semiconductor device further comprises a conductive pillar on the first substrate and in the first molding compound, wherein the conductive pillar comprises a non-conductive pillar core and a conductive pillar shell on the pillar core.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor device, comprising:
a base assembly comprising
a first substrate,
a first device on a top surface of the first substrate, and
a first encapsulant on the top surface of the first substrate and bounding a side surface of the first device; and
a conductive pillar on the first substrate and in the first encapsulant;
wherein:
the conductive pillar comprises a non-conductive pillar core and a conductive pillar shell on the non-conductive pillar core; and
the non-conductive pillar core does not extend above a top side of the first encapsulant.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a conductor on a top end of the non-conductive pillar core.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the conductor and the conductive pillar shell comprise the same material.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the conductor comprises a portion of the conductive pillar shell.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein a top end of the non-conductive pillar core is below a top side of the first encapsulant.

### Claim 7 (depends on 2)

The semiconductor device of claim 2, wherein:
a top end of the conductive pillar shell is exposed from the first encapsulant; and
a top end of the non-conductive pillar core is covered by the top end of the conductive pillar shell.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, further comprising:
a top assembly comprising
a second substrate,
a second device on a top surface of the second substrate, and
a second encapsulant on the top surface of the second substrate and bounding a side surface of the second device, and
an interconnect on a bottom surface of the second substrate;
wherein the interconnect couples the second substrate with a top end of the conductive pillar.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
an interface layer between the top assembly and the base assembly, the interface layer bounding the interconnect of the top assembly.

### Claim 10 (depends on 2)

The semiconductor device of claim 2, wherein:
a top end of the first encapsulant is substantially coplanar with a top end of the conductive pillar; and
the top end of the conductive pillar extends further from the top surface of the first substrate than a top end of the first device.

### Claim 11 (depends on 2)

The semiconductor device of claim 2, wherein:
a top end of the first encapsulant is substantially coplanar with a top end of the conductive pillar and a top end of the first device.

### Claim 12 (depends on 2)

The semiconductor device of claim 2, wherein:
a width of the non-conductive pillar core is greater than a thickness of the conductive pillar shell;
the width of the non-conductive pillar core is approximately 50 microns to approximately 200 microns; and
the thickness of the conductive pillar shell is approximately 10 microns to approximately 50 microns.

### Claim 13

A method to manufacture a semiconductor device, comprising:
providing a pillar core of non-conductive material on a top surface of a first substrate;
providing a pillar shell on the pillar core to form a conductive pillar;
placing a first device on the top surface of the first substrate; and
providing a first encapsulant on the top surface of the first substrate to contact a side surface of the first device and the conductive pillar;
wherein the pillar core does not extend above a top side of the first encapsulant.

### Claim 14 (depends on 13)

The method of claim 13, further comprising providing a conductor on a top end of the pillar shell.

### Claim 15 (depends on 14)

The method of claim 14, wherein the conductor and the pillar shell comprise the same material.

### Claim 16 (depends on 14)

The method of claim 14, wherein the conductor comprises a portion of the pillar shell.

### Claim 17 (depends on 13)

The method of claim 13, wherein a top end of pillar core is below a top side of the first encapsulant.

### Claim 18 (depends on 13)

The method of claim 13, wherein:
providing the pillar core comprises:
providing a non-conductive material on the top surface of the first substrate; and
removing a portion of the non-conductive material to define the pillar core; and
the pillar core is in direct contact with a pad of the first substrate.

### Claim 19

A method to manufacture a semiconductor device, comprising:
providing a redistribution layer (RDL) substrate on a carrier, wherein the RDL substrate comprises a dielectric structure and a redistribution structure in the dielectric structure;
providing a non-conductive material on a top surface of the RDL substrate;
removing a portion of the non-conductive material to form a pillar core;
providing a pillar shell on the pillar core to form a conductive pillar electrically coupled with the redistribution structure;
placing a device on the RDL substrate to contact the redistribution structure;
providing an encapsulant on the top surface of the RDL substrate and in contact with a side surface of the device; and
removing the carrier and providing an interconnect on a bottom surface of the RDL substrate electrically coupled with the redistribution structure;
wherein the pillar core does not extend above a top side of the encapsulant.

### Claim 20 (depends on 19)

The method of claim 19, further comprising providing a conductor on a top end of the pillar core.

### Claim 21 (depends on 20)

The method of claim 20, wherein the conductor and the pillar shell comprise the same material.