# US 2022/0045035 A1 · Semiconductor devices and manufacturing methods of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0045035 A1 - Document ID: US20220045035A1 - Status: Published application - Kind: A1 - Application number: 17/510,594 - Filed: 2021-10-26 - Published: 2022-02-10 - Earliest claimed: 2018-10-01 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyun Mog PARK - Web page: https://patentgrep.com/patent/US20220045035A1 ## CPC - H10D 88/00: Three-dimensional [3D] integrated devices - H10W 90/00: Package configurations - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/30: characterised by the memory core region - H10B 41/40: characterised by the peripheral circuit region - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/30: characterised by the memory core region - H10B 43/40: characterised by the peripheral circuit region - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 88/01: {Manufacture or treatment} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 72/00: Interconnections or connectors in packages - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 72/90: Bond pads, in general - H10W 72/941: {Dispositions of bond pads} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 80/016: {Cleaning} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising: forming a first substrate structure by forming first gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a first substrate, first channels extending perpendicular to the first substrate while passing through the first gate electrodes, first bit lines connected to the first channels, and first bonding pads disposed on the first bit lines to be electrically connected to the first bit lines, respectively, on the first substrate; forming a second substrate structure by forming second gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a second substrate, second channels extending perpendicular to the second substrate while passing through the second gate electrodes, second bit lines connected to the second channels, and second bonding pads disposed on the second bit lines to be electrically connected to the second bit lines, respectively, on the second substrate; forming a third substrate structure by forming circuit elements on a third substrate, through contact plugs passing through the third substrate to a predetermined depth, and third bonding pads disposed on the circuit elements, on a first surface of the third substrate; bonding the third substrate structure to the first substrate structure by bonding the first bonding pads to the third bonding pads; exposing first ends of the through contact plugs by removing a portion of the third substrate from a second surface of the third substrate, opposite the first surface of the third substrate; forming fourth bonding pads on the through contact plugs, exposed through the second surface of the third substrate; and bonding the second substrate structure to the third substrate structure by bonding the second bonding pads to the fourth bonding pads. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the first bit lines are electrically connected to the second bit lines through the first bonding pads, the third bonding pads, the through contact plugs, the fourth bonding pads, and the second bonding pads. ### Claim 3 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein: the forming the first to third substrate structures further includes forming first to fourth dielectric layers surrounding the first to fourth bonding pads, respectively, in the bonding the third substrate structure to the first substrate structure, the first dielectric layer is bonded to the third dielectric layer, and in the bonding the second substrate structure to the third substrate structure, the fourth dielectric layer is bonded to the second dielectric layer. ### Claim 4 (depends on 3) The method for manufacturing a semiconductor device of claim 3, wherein each of the first to fourth dielectric layers is a diffusion prevention layer preventing diffusion of materials of the first to fourth bonding pads. ### Claim 5 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein each of the first channels has an inclined side surface narrowing toward the first substrate and each of the second channels has an inclined side surface narrowing toward the second substrate. ### Claim 6 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the first substrate structure and the second substrate structure have a symmetrical structure based on the third substrate structure. ### Claim 7 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the forming the third substrate structure includes: forming contact holes by removing a portion of the third substrate; forming a substrate insulating layer on a side wall and a lower surface of the third substrate exposed through the contact holes; and filling the contact holes with a conductive material to form the through contact plugs. ### Claim 8 (depends on 1) The method for manufacturing a semiconductor device of claim 1, wherein the first gate electrodes are electrically connected to the second gate electrodes through the first bonding pads, the third bonding pads, the through contact plugs, the fourth bonding pads, and the second bonding pads. ### Claim 9 A method for manufacturing a semiconductor device, comprising: forming a first substrate structure; forming a second substrate structure; and bonding the second substrate structure to the first substrate structure, wherein the forming the first substrate structure includes: forming a first stacked structure of first sacrificial layers and first interlayer insulating layers alternately stacked on a first substrate; forming first channels passing through the first stacked structure; forming first openings passing through the first stacked structure; removing the first sacrificial layers through the first openings; forming first gate electrodes by filling regions from which the first sacrificial layers are removed with a conductive material; forming first bit lines connected to the first channels; and forming first bonding pads on the first bit lines to be electrically connected to the first bit lines, wherein the forming the second substrate structure includes: forming a second stacked structure of second sacrificial layers and second interlayer insulating layers alternately stacked on a second substrate; forming second channels passing through the second stacked structure; forming second openings passing through the second stacked structure; removing the second sacrificial layers through the second openings; forming second gate electrodes by filling regions from which the second sacrificial layers are removed with a conductive material; forming second bit lines connected to the second channels; and forming second bonding pads on the second bit lines to be electrically connected to the second bit lines, wherein the bonding the second substrate structure to the first substrate structure includes bonding the first bonding pads and the second bonding pads, and wherein the first bit lines are electrically connected to the second bit lines, respectively, through the first bonding pads and the second bonding pads. ### Claim 10 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein the bonding the first bonding pads and the second bonding pads is performed by applying a pressure without intervention of an adhesive. ### Claim 11 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein each of the first bit lines is electrically connected to each of the second bit lines arranged to vertically overlap each other. ### Claim 12 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein: the forming the first substrate structure further includes forming first lower contact plugs between the first channels and the first bit lines, and the forming the second substrate structure further includes forming first upper contact plugs between the second channels and the second bit lines. ### Claim 13 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein: the forming the first substrate structure further includes forming second lower contact plugs between the first bonding pads and the first bit lines, and the forming the second substrate structure further includes forming second upper contact plugs between the second bonding pads and the second bit lines. ### Claim 14 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein: the forming the first substrate structure further includes removing a portion of the first sacrificial layers to allow the first gate electrodes to be extended by different lengths in the forming the first gate electrodes, to provide contact regions at ends of the first gate electrodes, and the forming the second substrate structure further includes removing a portion of the second sacrificial layers to allow the second gate electrodes to be extended by different lengths in the forming the second gate electrodes, to provide contact regions at ends of the second gate electrodes. ### Claim 15 (depends on 14) The method for manufacturing a semiconductor device of claim 14, wherein the forming the first substrate structure further includes: forming first cell contact plugs extending perpendicular to a surface of the first substrate and connected to the first gate electrodes, respectively, in the contact regions of the first gate electrodes, and forming third bonding pads disposed on the first cell contact plugs so that the first cell contact plugs are between the first gate electrodes and the third bonding pads, respectively, wherein the forming the second substrate structure further includes: forming second cell contact plugs extending perpendicular to a surface of the second substrate and connected to the second gate electrodes, respectively, in the contact regions of the second gate electrodes, and forming fourth bonding pads disposed on the second cell contact plugs so that the second cell contact plugs are between the second gate electrodes and the fourth bonding pads, respectively, and wherein the third bonding pad and the fourth bonding pad are bonded to each other. ### Claim 16 (depends on 15) The method for manufacturing a semiconductor device of claim 15, wherein the third bonding pads and the fourth bonding pads electrically connect the first cell contact plugs to the second cell contact plugs. ### Claim 17 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein the first gate electrodes and the second gate electrodes as well as the first channels and the second channels are disposed symmetrically based on an interface between the first substrate structure and the second substrate structure. ### Claim 18 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein the forming the first substrate structure further includes: forming a base substrate; forming circuit elements on the base substrate; and forming the first substrate on the circuit elements. ### Claim 19 (depends on 18) The method for manufacturing a semiconductor device of claim 18, wherein the base substrate and the second substrate include a single crystalline layer, and the first substrate includes a polycrystalline layer or an epitaxial layer. ### Claim 20 (depends on 9) The method for manufacturing a semiconductor device of claim 9, wherein: the forming the first substrate structure further includes forming a first dielectric layer surrounding the first bonding pads, and the forming the second substrate structure further includes forming a second dielectric layer surrounding the second bonding pads, wherein the bonding the second substrate structure to the first substrate structure includes bonding the first dielectric layer and the second dielectric layer.