# US 2022/0045034 A1 · Devices, systems, and methods for stacked die packages

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0045034 A1
- Document ID: US20220045034A1
- Status: Published application
- Kind: A1
- Application number: 17/392,995
- Filed: 2021-08-03
- Published: 2022-02-10
- Earliest claimed: 2020-08-04
- Assignees: Flex Ltd.
- Applicants: Flex Ltd.
- Inventors: Cheng Yang; Dongkai Shangguan
- Web page: https://patentgrep.com/patent/US20220045034A1

## CPC

- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/075: {of bond wires}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/327: {Multiple die-attach connectors having different sizes}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/853: {On the same surface}
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.

## Claims

### Claim 1

A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and
a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view.

### Claim 2 (depends on 1)

The package of claim 1, wherein the first electrical contact is located at a first side of the second chip.

### Claim 3 (depends on 2)

The package of claim 2, further comprising:
a second electrical contact on the second chip and located at a second side of the second chip opposite the first side of the second chip.

### Claim 4 (depends on 3)

The package of claim 3, wherein at least a portion of the second electrical contact does not overlap with the first chip in the plan view.

### Claim 5 (depends on 1)

The package of claim 1, wherein, in a cross sectional view, a width of the first chip is less than a width of the second chip.

### Claim 6 (depends on 1)

The package of claim 1, further comprising:
a second chip stack adhered to the first chip stack and including:
a third chip including third bonding structures;
a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and
a second electrical contact on the fourth chip, wherein at least a portion of the second electrical contact does not overlap with the third chip in the plan view; and
a support substrate that supports the first chip stack and the second chip stack.

### Claim 7 (depends on 6)

The package of claim 6, wherein, in a cross sectional view, a width of the first chip is less than a width of the second chip, and a width of the third chip is less than a width of the fourth chip, and wherein the first electrical contact and the second electrical contact overlap one another in the plan view.

### Claim 8 (depends on 6)

The package of claim 6, wherein the first chip stack and the second chip stack are aligned with one another.

### Claim 9 (depends on 8)

The package of claim 8, wherein the portion of the second electrical contact does not overlap the first chip in the plan view.

### Claim 10 (depends on 6)

The package of claim 6, wherein the first chip stack and the second chip stack are offset from one another.

### Claim 11 (depends on 6)

The package of claim 6, further comprising:
a first bonding wire electrically connected to the first electrical contact; and
a second bonding wire electrically connected to the second electrical contact.

### Claim 12 (depends on 11)

The package of claim 11, wherein the first electrical contact and the second electrical contact overlap in the plan view.

### Claim 13 (depends on 1)

The package of claim 1, wherein the first chip or the second chip, or both, is a reconstituted chip.

### Claim 14

A method, comprising:
forming a plurality of grooves in a first wafer including a plurality of first chips;
bonding the first wafer to a second wafer including a plurality of second chips to form a bonded structure;
thinning the first wafer in the bonded structure to remove the plurality of grooves; and
dicing the thinned bonded structure to form a plurality of first chip stacks, each first chip stack including one of the first plurality of chips and one of the second plurality of chips.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first wafer includes a plurality of first bonding structures bonded to a plurality of second bonding structures included on the second wafer.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
forming electrical contacts on the second wafer in regions that overlap the plurality of grooves.

### Claim 17 (depends on 16)

The method of claim 16, wherein thinning the first wafer to remove the plurality of grooves exposes the electrical contacts in the bonded structure.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
attaching bonding wires to the electrical contacts exposed by the thinning.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
adhering a plurality of second chip stacks to the plurality of first chip stacks to form a plurality of packages.

### Claim 20

A package, comprising:
a first chip stack including:
a first chip including first bonding structures;
a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and
a first electrical contact on the second chip, wherein the first electrical contact does not overlap with the first chip in a plan view; and
a second chip stack adhered to the first chip stack and including:
a third chip including third bonding structures;
a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and
a second electrical contact on the fourth chip, wherein the second electrical contact does not overlap with the third chip in the plan view; and
a support substrate that supports the first chip stack and the second chip stack.